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参数资料
| 型号： | ST7FLITE09Y0B3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封装： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件页数： | 59/115页 |
| 文件大小： | 781K |
| 代理商： | ST7FLITE09Y0B3 |
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ST7FLITE0
48/115
LITE TIMER (Cont’d)
11.1.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = ICIE
Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF
Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 5 = TB
Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
MHz)
Bit 4 = TBIE
Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF
Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF
Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
Bit 1 = WDGE
Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD
Watchdog Reset Delay
This bit is set by software. It is cleared by hard-
ware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE
TIMER
INPUT
CAPTURE
REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bit 7:0 = ICR[7:0]
Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Table 13. Lite Timer Register Map and Reset Values
70
ICIE
ICF
TB
TBIE
TBF
WDGR WDGE WDGD
70
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Address
(Hex.)
Register
Label
765
4
321
0
0B
LTCSR
Reset Value
ICIE
0
ICF
x
TB
0
TBIE
0
TBF
0
WDGRF
0
WDGE
0
WDGD
0
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
1
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相关代理商/技术参数 |
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|---|---|
| ST7FLITE09Y0B6 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST7FLITE09Y0B6 | 制造商:STMicroelectronics 功能描述:IC 8BIT FLASH MCU 7FLITE09 DIP16 |
| ST7FLITE09Y0B6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7FLITE09Y0M3 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST7FLITE09Y0M6 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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