![](http://datasheet.mmic.net.cn/120000/ST7MC1K2T6-XXX_datasheet_3577044/ST7MC1K2T6-XXX_209.png)
ST7MC1/ST7MC2
209/308
MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER A (MCRA)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = MOE: Output Enable bit.
0: Outputs disabled
1: Outputs enabled
Notes:
– The reset state is either high impedance, high or
low state depending on the corresponding option
bit.
– When the MOE bit in the MCRA register is reset
(MCOx outputs in reset state), and the SR bit in
the MCRA register is reset (sensorless mode)
and the SPLG bit in the MCRC register is reset
(sampling at PWM frequency) then, depending
on the state of the ZSV bit in the MSCR register,
Z event sampling can run or be stopped (and D
event is sampled).
Bit 6 = CKE: Clock Enable Bit.
0: Motor Control peripheral Clocks disabled
1: Motor Control peripheral Clocks enabled
Note: Clocks disabled means that all peripheral in-
ternal clocks (Delay manager, internal sampling
clock, PWM generator) are disabled. Therefore,
the peripheral can no longer detect events and the
preload registers do not operate.
When Clocks are disabled, write accesses are al-
lowed, so for example, MTIM counter register can
be reset by software.
Table 56. Output configuration summary
Note 1: “Peripheral frozen” configuration is not
recommended, as the peripheral may be stopped
in a unknown state (depending on PWM generator
outputs,etc.). It is better practice to exit from run
mode by first setting output state (by toggling ei-
ther MOE or DAC bits) and then to disabling the
clock if needed.
Note 2: In Direct Access Mode (DAC=1), when
CKE=0 (Peripheral Clock disabled) only logical
level can be applied on the MCOx outputs when
they are enabled whereas when CKE=1 (Peripher-
al Clock enabled), a PWM signal can be applied
Note 3: When clocks are disabled (CKE bit reset)
while outputs are enabled (MOE bit set), the ef-
fects on the MCOx outputs where PWM signal is
applied depend on the running mode selected:
– in voltage mode (VOC1 bit=0), the MCOx out-
puts where PWM signal is applied stay at level 1.
– in current mode (VOC1 bit=1), the MCOx outputs
where PWM signal is applied are put to level 0.
In all cases, MCOx outputs where a level 1 was
applied before disabling the clocks stay at level 1.
That is why it is recommended to disable the
MCOx outputs (reset MOE bit) before disabling the
clocks. This will put all the MCOx outputs under re-
set state defined by the corresponding option bit.
76
54
32
10
MOE
CKE
SR
DAC
V0C1
SWA
PZ
DCB
MOE bit
MCO[5:0] Output pin
State
0
Reset state
1
Output enabled
CKE
bit
MOE
bit
DAC
bit
Peripheral
Clock
Effect on MCOx
Output
0
x
Disabled
Reset state
0
1
0
Disabled
Peripheral frozen (see
note 1 below)
0
1
Disabled
Direct access via
MPHST
(only logical level)
1
0
x
Enabled
Reset state
1
0
Enabled
Standard
running mode.
1
Enabled
Direct access via
MPHST (PWM can be
applied)
1