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参数资料
| 型号： | ST7PLU09MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 86/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU09MAE |
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On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog
reset will not occur for at least 2ms.
Note:
Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
Caution:
When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is
enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware Watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the option byte description in Chapter 14: Device configuration and ordering
Using Halt mode with the Watchdog (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
Timer stops counting and is no longer able to generate a Watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset
is generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Figure 29.
Watchdog timing diagram
tWDG
fWDG
INTERNAL
WATCHDOG
RESET
WDGD BIT
SOFTWARE SETS
WDGD BIT
HARDWARE CLEARS
WDGD BIT
WATCHDOG RESET
(2ms @ 8 MHz fOSC)
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