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参数资料
| 型号： | ST7PLU09MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 88/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU09MAE |
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On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
10.1.6
Register description
Lite timer control/status register (LTCSR)
LTCSR
Reset value: 0000 0x00 (0xh)
7
654
32
10
ICIE
ICF
TB
TBIE
TBF
WDGR
WDGE
WDGD
R/W
Table 35.
LTCSR register description
Bit
Name
Function
7ICIE
Interrupt enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
6ICF
Input Capture flag
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR
register
5TB
Timebase period selection
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)
4TBIE
Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
3TBF
Timebase Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register.
Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
2
WDGRF
Force Reset/Reset Status flag
This bit is used in two ways: It is set by software to force a watchdog reset. It is set
by hardware when a watchdog reset occurs and cleared by hardware or by
software. It is cleared by hardware only when an LVD reset occurs. It can be
cleared by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
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