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参数资料
| 型号： | ST7PLU09MCTRE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 93/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU09MCTRE |
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On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
Figure 33.
PWM signal example
Output compare mode
To use this function, the OE bit must be 0, otherwise the compare is done with the shadow
register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded immediately (without waiting for an OVF
event).
The DCR0H must be written first, the output compare function starts only when the DCR0L
value is written.
When the 12-bit up counter (CNTR) reaches the value stored in the DCR0H and DCR0L
registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is
generated if the CMPIE bit is set.
Note:
The output compare function is only available for DCRx values other than 0 (reset value).
Caution:
At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value
has not yet been written (in this case, the shadow register will contain the new DCR0H value
and the old DCR0L value), then:
- If OE = 1 (PWM mode): the compare is done between the timer counter and the shadow
register (and not DCRx)
- if OE = 0 (OCMP mode): the compare is done between the timer counter and DCRx. There
is no PWM signal.
The compare between DCRx or the shadow register and the timer counter is locked until
DCR0L is written.
10.2.4
Low power modes
COUNTER
PWM0
OUTPUT
t
WITH
OE0
=
1
A
ND
OP0
=
0
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0 = FFEh
ATR = FFDh
fCOUNTER
Table 38.
Effect of low power modes on AT timer
Mode
Description
Slow
The input frequency is divided by 32
Wait
No effect on AT timer
Active Halt
AT timer halted except if CK0 = 1, CK1 = 0 and OVFIE = 1
Halt
AT timer halted
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