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ST90158 - I/O PORTS
8.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
8.5.1 Pin Declared as I/O
A pin declared as I/O, is connected to the I/O buff-
er. This pin may be an Input, an Output, or a bidi-
rectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
8.5.2 Pin Declared as an Alternate Input
A single pin may be directly connected to several
Alternate inputs. In this case, the user must select
the required input mode (with the PxC2, PxC1,
PxC0 bits) and enable the selected Alternate
Function in the Control Register of the peripheral.
No specific port configuration is required to enable
an Alternate Function input, since the input buffer
is directly connected to each alternate function
module on the shared pin. As more than one mod-
ule can use the same input, it is up to the user soft-
ware to enable the required module as necessary.
Parallel I/Os remain operational even when using
an Alternate Function input. The exception to this
is when an I/O port bit is permanently assigned by
hardware as an A/D bit. In this case , after soft-
ware programming of the bit in AF-OD-TTL, the Al-
ternate function output is forced to logic level 1.
The analog voltage level on the corresponding pin
is directly input to the A/D.
8.5.3 Pin Declared as an Alternate Function
Output
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alter-
nate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
WARNING: When a pin is connected both to an al-
ternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
8.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For In-
terrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the in-
ternal memory is being used and the ports are act-
ing as I/O, the status is the same as shown for the
other I/O ports.
Mode
Ext. Mem - I/O Ports
I/O Ports
P0
P1, P2, P6
WFI
High Imped-
ance or next
address (de-
pending on
the last
memory op-
eration per-
formed on
Port)
Next
Address
Not Affected (clock
outputs running)
HALT
High Imped-
ance
Next
Address
Not Affected (clock
outputs stopped)
RESET
Alternate function push-
pull (ROMless device)
Bidirectional Weak
Pull-up (High im-
pedance when disa-
bled in hardware).
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