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SERIAL COMMUNICATIONS INTERFACE (SCI)
REGISTER DESCRIPTION (Cont’d)
Bit 0 = STPEN:
Stick Parity Enable.
0: The transmitter and the receiver will follow the
parity of even parity bit EP in the CHCR register.
1: The transmitter and the receiver will use the op-
posite parity type selected by the even parity bit
EP in the CHCR register.
BAUD RATE GENERATOR HIGH REGISTER
(BRGHR)
R252 - Read/Write
Reset value: undefined
BAUD RATE GENERATOR LOW REGISTER
(BRGLR)
R253 - Read/Write
Reset value: undefined
Bit 15:0 =
Baud Rate Generator MSB and LSB.
The Baud Rate generator is a programmable di-
vide by “N” counter which can be used to generate
the clocks for the transmitter and/or receiver. This
counter divides the clock input by the value in the
Baud Rate Generator Register. The minimum
baud rate divisor is 2 and the maximum divisor is
216-1. After initialization of the baud rate genera-
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load. If set to 0 or 1, the Baud
Rate Generator is stopped.
SYNCHRONOUS INPUT CONTROL (SICR)
R254 - Read/Write
Reset value: 0000 0011 (03h)
Bit 7 = SMEN:
Synchronous Mode Enable.
0: Disable all features relating to Synchronous
mode (the contents of SICR and SOCR are ig-
nored).
1: Select Synchronous mode with its programmed
I/O configuration.
Bit 6 = INPL:
SIN Input Polarity.
0: Polarity not inverted.
1: Polarity inverted.
Note: INPL only affects received data. In Auto-
Echo mode SOUT = SIN even if INPL is set. In
Loop-Back mode the state of the INPL bit is irrele-
vant.
Bit 5 = XCKPL:
Receiver Clock Polarity.
0: RXCLK is active on the rising edge.
1: RXCLK is active on the falling edge.
Note: XCKPL only affects the receiver clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the XCKPL status. In Loop-Back the state
of the XCKPL bit is irrelevant.
Bit 4 = DCDEN:
DCD Input Enable.
0: Disable hardware synchronization.
1: Enable hardware synchronization.
Note: When DCDEN is set, RXCLK drives the re-
ceiver section only during the active level of the
DCD input (DCD works as a gate on RXCLK, in-
forming the MCU that a transmitting device is
sending a synchronous frame to it).
Bit 3 = DCDPL:
DCD Input Polarity.
0: The DCD input is active when LOW.
1: The DCD input is active when HIGH.
Note: DCDPL only affects the gating activity of the
receiver clock. In Auto-Echo mode RTS = DCD in-
dependently of DCDPL. In Loop-Back mode, the
state of DCDPL is irrelevant.
EP
SPEN
Parity (Transmitter &
Receiver)
0 (odd)
0
Odd
1 (even)
0
Even
0 (odd)
1
Even
1 (even)
1
Odd
15
8
BG15
BG14
BG13
BG12
BG11
BG10
BG9
BG8
70
BG7
BG6
BG5
BG4
BG3
BG2
BG1
BG0
70
SMEN
INPL
XCKPL
DCDE
N
DCDP
L
INPEN
X
9