- 您现在的位置：买卖IC网 > PDF目录380730 > ST92163N4G0V (意法半导体) 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT PDF资料下载
参数资料
| 型号： | ST92163N4G0V |
| 厂商： | 意法半导体 |
| 英文描述： | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| 中文描述： | 16位产品全速USB微控制器16端点，20,000光盘和2K的RAM，I2C和脊髓损伤的复合设备， |
| 文件页数： | 184/224页 |
| 文件大小： | 1372K |
| 代理商： | ST92163N4G0V |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页当前第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页第224页
184/224
ST92163 - I2C BUS INTERFACE
I
2
C INTERFACE
(Cont’d)
Note
: Until the pending bit is reset (while the cor-
responding mask bit is set), the peripheral proc-
esses an interrupt request. So, if at the end of an
interrupt routine thepending bit is not reset, anoth-
er interrupt request is performed.
Note
: Before the end of the transmission and re-
ception interrupt routines, the I2CSR1.BTF flag bit
should be checked, to acknowledge any interrupt
requests that occurred during the interrupt routine
and to avoid masking subsequent interrupt re-
quests.
Note:
The “Error” event interrupt pending bit
(I2CISR.IERRP) is forced high until the error event
flags are set (ADD10, ADSL and SB flags of the
I2CSR1 register; SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags of the I2CSR2 register).
Note:
If the I2CISR.DMASTOP bit is reset, then
the DMA has the highest priority with respect to
the interrupts; if the bit is set (as after the MCU re-
set) and the “Error event” pending bit is set
(I2CISR.IERRP), then the DMA is suspended until
the pending bit is reset by software. In the second
case, the “Error” interrupt sources have higher pri-
ority, followed by DMA, “Data received” and “Re-
ceiving End Of Block” interrupts, “Peripheral
Ready to Transmit” and “Transmitting End Of
Block”.
Moreover the Transmitting End Of Block interrupt
has the same priority as the “Peripheral Ready to
Transmit” interrupt and the Receiving End Of
Block interrupt has the same priority as the “Data
received” interrupt.
8.5.6 DMA Features
The peripheral can use the ST9+ on-chip Direct
Memory Access (DMA) channels to provide high-
speed data transaction between the peripheral
and contiguous locations of Register File, and
Memory. The transactions can occur from and to-
ward the peripheral. The maximum number of
transactions that each DMA channel can perform
is 222 if the register file is selected or 65536 if
memory is selected. The control of the DMA fea-
tures is performed using registers placed inthe pe-
ripheral
register
page
I2CRDAP, I2CRDC, I2CTDAP, I2CTDC).
Each DMA transfer consists of three operations:
– A load from/to the peripheral data register
(I2CDR) to/from a location of Register File/Mem-
(I2CISR,
I2CIMR,
ory addressed through the DMA Address Regis-
ter (or Register pair)
– A post-increment of the DMA Address Register
(or Register pair)
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Depending on the value of the DDCISR.DMAS-
TOP bit the DMA feature can be suspended or not
(both in transmission and in reception) until the
pending bit related to the “Error event” interrupt re-
quest is set.
The priority level of the DMA features of the I
2
C
interface with respect to the other peripherals and
the CPU is the same as programmed in the
I2CISR register for the interrupt sources. In the in-
ternal priority level order of the peripheral, if DD-
CISR.DMASTOP=0, DMA has a higher priority
with respect to the interrupt sources. Otherwise (if
DDCISR.DMASTOP=1), the DMA has a priority
lower than “error” event interrupt sources but
greater than reception and transmission interrupt
sources.
Refer to the Interrupt and DMA chapters for details
on the priority levels.
The DMA features are enabled by setting the cor-
responding enabling bits (RXDM, TXDM) in the
I2CIMR register. It is possible to select also the di-
rection of the DMA transactions.
Once the DMA transfer is completed (the transac-
tion counter reaches 0 value), an interrupt request
to the CPU is generated. This kind of interrupt is
called “End Of Block”. The peripheral sends two
different “End Of Block” interrupts depending on
the direction of the DMA (Receiving End Of Block -
Transmitting End Of Block). These interrupt
sources have dedicated interrupt pending bits in
the I2CIMR register (REOBP, TEOBP) and they
are mapped on the same interrupt vectors as re-
spectively “DataReceived” and “Peripheral Ready
to Transmit” interrupt sources. The same corre-
spondence exists about the internal priority be-
tween interrupts.
Note
: The I2CCR.ITE bit has no effect on the End
Of Block interrupts.
Moreover, the I2CSR1.EVF flag is not set by the
End Of Block interrupts.
相关PDF资料 |
PDF描述 |
|---|---|
| ST92163R4G0V | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4T1V | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92E163R4T1V | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92T163R4T1V | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4B0 | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST92163N4G1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163N4G1E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163N4G1L | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163N4G1V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| ST92163R4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT |
发布紧急采购，3分钟左右您将得到回复。