参数资料
型号: ST92163N4G0V
厂商: 意法半导体
英文描述: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
中文描述: 16位产品全速USB微控制器16端点,20,000光盘和2K的RAM,I2C和脊髓损伤的复合设备,
文件页数: 186/224页
文件大小: 1372K
代理商: ST92163N4G0V
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186/224
ST92163 - I2C BUS INTERFACE
I
2
C INTERFACE
(Cont’d)
8.5.7 Register Description
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
2. Bit7 of the I2CCR registermust be cleared.
I
2
C CONTROL REGISTER (I2CCR)
R240 - Read / Write
Register Page: 20
Reset Value: 0000 0000 (00h)
Bit 7:6 =
Reserved
Must be cleared
Bit 5 =
PE
Peripheral Enable.
This bit is set and cleared by software.
0: Peripheral disabled (reset value)
1: Master/Slave capability
Notes:
– When I2CCR.PE=0, all the bits of the I2CCR
register and the I2CSR1-I2CSR2 registers ex-
cept the STOP bitare reset. All outputs willbe re-
leased while I2CCR.PE=0
– When I2CCR.PE=1, thecorresponding I/O pins
are selected by hardware as alternate functions
(open drain).
– Toenable theI
2
C interface, writethe I2CCR reg-
ister
TWICE
with I2CCR.PE=1 as the first write
only activates the interface (only I2CCR.PE is
set).
– WhenPE=1, the FREQ[2:0]and EN10BITbits in
the I2COAR2 and I2CADR registers cannot be
written. The value of these bits can be changed
only when PE=0.
Bit 4 =
ENGC
General Call address enable.
Setting this bit the peripheralworks as a slave and
the value stored in the I2CADR register is recog-
nized as device address.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: The address stored in the I2CADR register is
ignored (reset value)
1: The General Call address storedin the I2CADR
register will be acknowledged
Note:
The correct value (usually 00h) must be
written in the I2CADR register beforeenabling the
General Call feature.
Bit 3 =
START
Generation of a Start condition
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0) or when the Start condition is
sent (with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation (reset value)
1: Start generation when the bus is free
Bit 2 =
ACK
Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: No acknowledge returned (reset value)
1: Acknowledge returned after an address byte or
a data byte is received
Bit 1 =
STOP
Generation of a Stop condition
This bit is set and cleared by software. It is also
cleared by hardware in master mode. It is not
cleared
when
the
(I2CCR.PE=0). In slave mode, this bit must be set
only when I2CSR1.BTF=1.
– In master mode:
0: No stop generation
1: Stopgeneration after thecurrent byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In slave mode:
0: No stop generation (reset value)
1: Release SCL and SDA lines after the current
byte transfer (I2CSR1.BTF=1). In this mode the
STOP bit has to be cleared by software.
interface
is
disabled
7
0
0
0
PE
ENGC
START ACK STOP ITE
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