参数资料
型号: ST92186B3BK
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封装: PLASTIC, SDIP-32
文件页数: 11/148页
文件大小: 1664K
代理商: ST92186B3BK
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ST92186B - ON SCREEN DISPLAY CONTROLLER (OSD)
OSD CONTROLLER (Cont’d)
7.4.7.5 Serial mode
In serial mode, only 1 byte is used to describe the
character code or the attribute (Figure 52):
– If the most significant bit (Bit 7) of this byte is 0,
the byte represents a character code.
– If the most significant bit (Bit 7) of this byte is 1,
the byte represents a serial attribute. Then the
display controller uses Bit 6 to determine wheth-
er the attribute is a foreground serial attribute (Bit
6 = 0) or a background serial attribute (Bit 6 = 1).
A consequence of this structure is that in serial
mode, only the first 128 characters stored in the
font ROM can be accessed (the value of the 7
least significant bits of the character code = the
character number in font ROM).
The first two bytes of the row buffer describing the
row are displayed as border color. The first char-
acter to be displayed in serial mode is in fact the
3rd of the row buffer.
All the attributes (background and foreground) are
displayed as space with background color.
Let’s assume that the start address of the current
row buffer is 2p (even address).
In this case the character codes and attributes are
stored in the OSDRAM at the address 2p+5+z,
where z value is 1 to RCN (RCN is the row charac-
ter count defined in Section 7.4.7.2).
Character Code in Serial Mode
Address in Segment 22h: 2p + 5 + z. See Figure
52.
Bits 6:0 = CHC[6:0]
Character Code in serial
mode
The CHC[6:0] value points to one of the first 128
characters stored in the font ROM.
BACKGROUND SERIAL ATTRIBUTE
Address in Segment 22h: 2p + 5 + z. See Figure
52.
Bits 5:4 Reserved
Bits 3:0 = BP[3:0]
Background Palette pointer
The BP[3:0] value points to one of the 16 prede-
fined entries of the background palette for the
background color and the translucency.
For example, BP[3:0] = 0 points to the first back-
ground palette entry, 30h & 31h if the palette swap
bit PASW of the OSDDR register is reset (see reg-
isters description for more details).
Note: the display of the background serial attribute
is affected by the use of the Italics (see the fore-
ground serial attribute) and also by the “M” bit lo-
cated in the Background Palette (see Section
7.4.6.4 for further details).
70
0
CHC6
CHC5
CHC4
CHC3
CHC2
CHC1 CHC0
70
1
x
BP3
BP2
BP1
BP0
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