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参数资料
型号： ST92186B3BK
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PDIP32
封装： PLASTIC, SDIP-32
文件页数： 23/148页
文件大小： 1664K
代理商： ST92186B3BK
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ST92186B - ON SCREEN DISPLAY CONTROLLER (OSD)
OSD CONTROLLER (Cont’d)
FLAG BIT REGISTER (OSDFBR)
R250 - Read/Write
Register Page: 42
Reset Value: xxxx xxxx (xxh)
Bit 7 = BUFL
Buffer Flag bit
This bit indicates which Row Buffer of the OSD
RAM is being used by the Display.
The BUFL flag is automatically re-evaluated each
time the Scan & Event line matching condition is
fulfilled. In case the “TE” bit is reset (see the OS-
DER register), the “BUFL” flag remains un-
changed as NO row buffer change occurs.
0: The OSD displays the content of the second row
buffer (the one NOT pointed by the “first buffer
start address” value).
1: The OSD displays the content of the Row Buffer
location pointed by the “first buffer start address”
value.
Note: The BUFL flag is automatically reset when
the (DION,OSDE) bits are switching from any oth-
er value to (1,1); it will be set at the first Buffer
transfer (scan & event match and TE=1).
Bit 6 = VSY
Vsync status bit
This bit gives the status of the VSYNC input signal.
0: the VSYNC input signal is inactive.
1: the VSYNC input signal is active.
Note: The VSYNC signal polarity is compensated
to always provide VSY=1 during the vertical pulse.
Bit 5 = HSY
Hsync status bit
This bit gives the status of the internal HS signal
generated by the skew corrector and locked to the
external HSYNC signal.
0: The HS signal is inactive.
1: The HS signal is active.
Note: the HSYNC signal polarity is compensated
to provide HSY=1 during the horizontal pulse.
Note: HSY remains active during the whole “Line
Start Mute” timing which is software controlled
through both the DBLS bit and the LSM[2:0] value
(see OSDER and OSDMR registers).
Bit 4 = VSDL
Delayed Vertical Pulse status bit
This bit indicates the status of the VDPLS internal
signal (it is the delayed vertical pulse issued from
the programmable vertical delay unit as described
by the OSDDR register bits VD[3:0])
0: The VDPLS internal signal is inactive
1: The VDPLS internal signal is active
Note: the VDPLS signal polarity is compensated
to provide VSDL =1 during the vertical pulse.
Bit 3 = FIELD
Field status bit
This bit indicates the current TV field.
0: TV beam is in field 2 (even field)
1: TV beam is in field 1 (odd field)
Bit 2 = DINT
Display Interrupt flag bit
This bit is set by hardware when an OSD interrupt
occurs. This bit must be reset by Software.
Bit 1 = Reserved.
Bit 0 = SL8
Most Significant Bit of the Scan Line
counter
Refer to the description of the OSDSLR register.
70
BUFL
VSY
HSY
VSDL
FIELD
DINT
-
SL8
相关PDF资料
PDF描述
ST92195B2T1/XXX 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP64
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