INTRODUCTION TO STD80/STDM80
< Input/Output Cells >
SEC ASIC
1-3
STD80/STDM80
< Input/Output Cells >
There are about one thousand different I/O buffers.
Each I/O cell is implemented solely on the basic I/O
cell architecture which forms the periphery of the
masterslice.
A test logic is provided to enable the efficient
parametric (threshold voltage) testing on input buffers
including CMOS and TTL level converters, Schmitt
trigger input buffers, clock drivers and oscillator
buffers. Pull-up and pull-down resistors are optional
features.
Three basic types of output buffers (non-inverting,
tri-state and open drain) are available in a range of
driving capabilities from 1mA to 24mA for 5V drive
and 1mA to 16mA for 3.3V drive.Two levels of slew
rate controls are provided for each buffer type (except
1mA and 2mA buffers) to reduce output power/ground
bus noise and signal ringing, especially in
simultaneous switching outputs.
Bi-directional buffers are combinations of input buffers
and output buffers (tri-state or open drain) in a single
unit. The I/O structure has been fully characterized for
ESD protection and latch-up resistance.
For user’s convenience, STD80/STDM80 library
provides with three options of pull-down and pull-up
resistances respectively. They are 50K
,
100K
, and
200K
(The default value is 100K
).
I/O Cell Drive Options
To provide designers with the greater flexibility, each
I/O buffer can be selected among various current
levels (e.g., 1mA, 2mA, ..., 24mA). The choice of
current-level for I/O buffers affects their propagation
delay and current noise.
The slew rate control helps decrease the system noise
and output signal overshoot/undershoot caused by the
switching of output buffers. The output edge rate can
be slowed down by selecting the high slew rate control
cells. STD80/STDM80 provides three different sets of
output slew rate controls. Only one I/O slot is required
for any slew rate control options.
5V/3.3V Mixed I/O Cells
When designers intend to make transitions from 5V
supplies to low voltage system, STD80 offers a
solution of interfacing problems encountered in mixed
5V/3V environment. This solution provides great
flexibility to different devices communicating each
other. PCI and PCMCIA buffers are also available in
this solution. You can see this in the following figure.
Figure 1-1.
5V/3.3V Mixed I/O Cells in STD80
In STDM80, level shifters are available to provide
internal 3V core with great flexibility when it interfaces
with a 5V device. Refer to the figure below.
Figure 1-2.
5V/3.3V Mixed I/O Cells in STDM80
PCI Buffers
In addition to input, output, bi-directional, slew rate
controlled and Schmitt trigger I/O buffers, SEC ASIC
now offers PCI (Peripheral Component Interconnect)
I/O buffers. PCI is expected to be better suited to the
more complex and feature-rich design than the
existing local bus standards. 5V, 3.3V and Universal
PCI buffers are included in the library.
3.3V
Level
Shifter
5V
Internal
5V
Operation
STD80 I/O Cells
3.3V
Level
Shifter
5V
STD80 I/O Cells
3.3V
5V
Internal
3.3V
Operation
STDM80 I/O Cells
3.3V
5V
STDM80 I/O Cells
Level
Shifter
Level
Shifter