INTRODUCTION TO STD80/STDM80
EXTERNAL DESIGN INTERFACE CONSIDERATIONS
SEC ASIC
1-27
STD80/STDM80
Simultaneous Switching Outputs (SSOs)
If several output drivers switch from high to low
simultaneously, the ground bouncing level becomes
quite large because the current flowing through the
inductance L is the total sum of the transient current of
each output driver. The amount of total current and the
level of ground bounce are proportional to the number
of SSOs.
This ground bounce can cause two types of problems,
a noise margin reduction and a generation of noise
spike on the output pad.
NOISE MARGIN REDUCTION
The ground bounce can cause a noise margin
reduction when the same ground bus is used for both
input buffers and output drivers as shown in Figure
1-27. The Figure of SSOs. The noise margin reduction
can be explained using the circuit in the same figure.
As you can see, if outputs switch from high to low
simultaneously, it results in a ground bounce or the
rise of the chip ground level relative to system ground.
The rise appears as the input voltage Vin_a is below
V
IH
causing false triggering of the input buffer. Vin is, in
this case, not the same as Vin_a. Note that Vin is
measured relative to the system ground, while Vin_a is
measured relative to the local device ground.
This phenomenon is shown in Figure 1-26. Noise
Margin Reduction due to SSOs. For a low-to-high
transition, it is the low input levels (V
IL
) that are
affected.
Figure 1-26.
Noise Margin Reduction due to
SSOs
NOISE SPIKE GENERATION ON STABLE OUTPUT
If input and output power buses are separated, the
problem of a noise margin reduction in the input buffer
can be solved. However, ground bounce can cause
another problem in spite of using separated power and
ground bus.
The Figure 1-28. Noise Spike Induced by Ground
Bounce shows a common octal driver application
where ground bounce spikes will be observable on the
one stable output. If the spike is considered as high by
another chip, this ground bounce may upset that
operation of interfacing device or cause system logic
errors.
Vin_a
V
IH
V
IL
V
SS
2.0V
0.8V
Figure 1-27.
The Figure of SSOs
i
C
L
i
C
L
i
C
L
i
C
L
nxi
Vin
Vin_a
System Ground
Input Receiver
SSOs
Chip Ground (Vn)
Chip Power
Internal Logic