JTAG TAP CONTROLLER MACROFUNCTION
JTAG BOUNDARY SCANS
STD80/STDM80
7-28
SEC ASIC
JTAG TAP CONTROLLER MACROFUNCTION
TAP controller macrofunction consists of instruction register and data register scan paths, a bypass register,
multiplexers and a 16-state finite state machine. The bypass register and instruction register are JTAG
devices. TAP controller uses the largest available internal buffers (IVD8) to drive data register control
signals.
Instruction register/decoder are external to TAP controller since the register length and instruction codes
vary from one ASIC design to another. The instruction register consists of three JTINT1 macrocells. The
instruction decoder is used to implement a minimum TAP configuration with a boundary scan register and
an optional identification register.
TAP Controller Input Pin Description
Name
BPSEL
DREGDI
IREGDI
TCK
TDI
TMS
Mandatory
Description
Bypass select
Data register scan path data-in
Instruction register scan path data-in
Test clock
Test data input to the bypass register
Test mode select controlling state transitions of a finite state
machine
Test reset input
TRSTN
TAP Controller Output Pin Description
Name
DRE
IRE
RSTO
SHFDR
SHFIR
TDO
TDOE
UPDATEDR
UPDATEIR
Mandatory
Description
Data register enable control output
Instruction register enable control output
Reset output
Data register shift control output
Instruction register shift control output
Test data output
TDO tri-state enable output
Data register update control output
Instruction register update control output
The bulleted pins (TCK, TDI, TMS and TDO) are mandatory pins associated with the IEEE P1149.1
standard test bus interface. TRSTN is an optional test reset input. It is possible to implement TAP without the
test reset input indicated in the IEEE P1149.1 standard by setting TRSTN pin to high logic state.
Alternatively, if a power-on reset capability is desired, TRSTN pin should be set to active low and connected
to the power-on reset circuitry.
The 16 states of the finite state machine, diagrammed in the figure 9-3, also comply with the proposed IEEE
P1149.1 standard. State transitions occur on the rising edge of TCK and are controlled by TMS. To ensure
stable state transitions, TMS transitions occur on the falling edges of TCK. Capture, shift or update of test
data take place on the next rising edge of TCK after the state transition or on each subsequent rising edge
of TCK if no state transition occurs.