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参数资料
| 型号： | STEL-1173/CM |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 2/11页 |
| 文件大小： | 188K |
| 代理商： | STEL-1173/CM |
STEL-1173
10
A spectral plot of the NCO output after conversion
with a DAC (Sony CX20202A-1) is shown below. In
this case, the clock frequency is 50 MHz and the output
frequency is programmed to 6.789 MHz. This 10-bit
DAC gives better performance than any of the
currently available 12-bit DACs at clock frequencies
higher than 10 or 20 MHz.
The maximum non-
harmonic spur level observed over the output
frequency range shown in this case is –74 dBc. The
spur levels are limited by the dynamic linearity of the
DAC. It is important to remember that when the
output frequency exceeds 25% of the clock frequency,
the second harmonic frequency will be higher than the
Nyquist frequency, 50% of the clock frequency. When
this happens, the image of the harmonic at the
frequency fc– 2fo, which is not harmonically related to
the output signal, will become intrusive since its
frequency falls as the output frequency rises,
eventually crossing the fundamental output when its
frequency crosses through fc/3. It would be necessary
to select a DAC with better dynamic linearity to
improve the harmonic spur levels. (The dynamic
linearity of a DAC is a function of both its static
linearity and its dynamic characteristics, such as
settling time and slew rates.)
At higher output
frequencies the waveform produced by the DAC will
have large output changes from sample to sample. For
this reason, the settling time of the DAC should be
short in comparison to the clock period. As a general
rule, the DAC used should have the lowest possible
glitch energy as well as the shortest possible settling
time.
TYPICAL SPECTRUM
Center Frequency:
6.7 MHz
Frequency Span:
10.0 MHz
Reference Level:
–5 dBm
Resolution Bandwidth: 1 KHz
Video Bandwidth:
3 kHz
Scale:
Log, 10 dB/div
Output frequency:
6.789 MHz
Clock frequency:
50 MHz
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