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参数资料
| 型号： | STEL-1173/CM |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 8/11页 |
| 文件大小： | 188K |
| 代理商： | STEL-1173/CM |
STEL-1173
6
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device.
Exposure of the device to these conditions for extended periods may also affect device reliability. All
voltages are referenced to V
SS.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–40 to +125
°C (Plastic package)
VDDmax
Supply voltage on VDD
–0.3 to + 7
volts
VI(max)
Input voltage
–0.3 to VDD + 0.3
volts
Ii
DC input current
± 10
mA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Range Units
VDD
Supply Voltage
+5
± 5%
Volts
(Commercial)
Ta
Operating Temperature (Ambient)
0 to +70
°C
(Commercial)
OUTPUT SIGNALS
OUT
11-0
The signal appearing on the OUT
11-0 bus is derived
from the 13 most significant bits of the phase
accumulator. The 12-bit sine or cosine function is
presented in offset binary or two's complement
format, depending on the status of the TWOSCOMP
input. When the phase accumulator is zero, e.g., after
a reset, the decimal value of the output is 2049 in offset
binary and 1 in two's complement. The nominal phase
(in degrees) of the sine wave output may be
determined at any point by multiplying the decimal
equivalent of the 13 most significant bits of the phase
accumulator by (360/8192) and then adding
(360/16384). OUT
11 is the MSB, and OUT0 is the LSB.
CARRY OUT
Each time the contents of the phase accumulator
exceeds the maximum value that can be represented
by a 48 bit number the CARRY OUT signal goes high
for one clock cycle.
SYNC
The normally high SYNC output goes low for one
clock cycle, 20 clock cycles after a LDSTB command, to
indicate the end of the pipeline delay and the start of
the new steady state condition.
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