参数资料
型号: STEL-1173/CM
厂商: INTEL CORP
元件分类: 数字信号处理外设
英文描述: 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44
封装: PLASTIC, LCC-44
文件页数: 4/11页
文件大小: 188K
代理商: STEL-1173/CM
STEL-1173
2
FUNCTIONAL DESCRIPTION
The STEL-1173 Numerically Controlled Oscillator
(NCO) uses digital techniques to provide a cost-
effective solution for low noise signal sources. The
NCO device combines low power 1.5
CMOS
technology with a unique architectural design resulting
in a power efficient, high-speed sinusoidal waveform
generator able to achieve fine tuning resolution and
exceptional spectral purity with clock frequencies up to
50 MHz.
The NCO generates digital sine or cosine functions of
very precise frequency to be used directly in digital
signal processing applications or, in conjunction with a
D/A converter, in analog frequency generation
applications. The NCO is designed to interface with
and be controlled from an 8-bit microprocessor bus.
The NCO maintains a record of phase which is accurate
to 48 bits. At each clock cycle, the number stored in the
48 bit
-Phase register is added to the previous value of
the phase accumulator. The number in the phase
accumulator represents the current phase of the
synthesized sine and cosine functions. The number in
the
-Phase register represents the change of phase for
each cycle of the clock. This number is directly related
to the output frequency by the following:
fc x -Phase
fo=
248
where: fo is the frequency of the output signal
and: fc is the clock frequency.
FEATURES
s 48-BIT FREQUENCY RESOLUTION
s 50 MHz CLOCK FREQUENCY (0 TO 70
°C)
s SINE OR COSINE OUTPUT AVAILABLE
s 12-BIT AMPLITUDE RESOLUTION AND
13-BIT PHASE RESOLUTION GIVES HIGH
SPECTRAL PURITY, ALL SPURS <–75 dBc
(AT DIGITAL OUTPUT)
s MICROPROCESSOR BUS COMPATIBLE
CONTROL INPUTS
s CASCADABLE ACCUMULATOR FOR
HIGHER FREQUENCY RESOLUTION
s 2's COMPLEMENT OR OFFSET BINARY
OUTPUT CODES
s LOW POWER CMOS
s MILITARY AND COMMERCIAL
TEMPERATURE RANGES AVAILABLE
APPLICATIONS
s FREQUENCY SYNTHESIZERS
s SINGLE SIDEBAND CONVERTERS
s BASEBAND RECEIVERS
s DIGITAL SIGNAL PROCESSORS
s HIGH SPEED HOPPED FREQUENCY
SOURCES
LDSTB
–PHASE
REGISTER
RESET
CLOCK
OUT 11-0
WRN
ADDR 2-0
DATA 7-0
8
ADDR.
SELECT
LOGIC
3
48
48–BIT
PHASE
ACCUMU-
LATOR
13
SINE
LOOKUP
TABLE
12
–PHASE
BUFFER
REGISTERS
48
6
CSN
BLOCK DIAGRAM
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