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参数资料
| 型号： | STEL-1173/CM |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 6/11页 |
| 文件大小： | 188K |
| 代理商： | STEL-1173/CM |
STEL-1173
4
FUNCTION BLOCK DESCRIPTION
ADDRESS SELECT LOGIC BLOCK
This block controls the writing of data into the device
via the DATA7-0 inputs. The data is written into the
device on the rising edge of the WRN input, and the
register into which the data is written is selected by the
ADDR2-0 inputs. The writing of data is also controlled
with the CSN input; this input must be low to enable
writing.
BUFFER REGISTER BLOCK
The Buffer Register is used to temporarily store the
-
Phase data written into the device. This allows the data
to be written asynchronously as six bytes per
48-bit
-Phase word. The data is transferred from this
register into the
-PhaseRegisterafterafallingedgeon
the LDSTB input.
-PHASE REGISTER BLOCK
This block controls the updating of the
-Phase word
used in the Accumulator. The frequency data from the
Buffer Register Block is loaded into this block after a
falling edge on the LDSTB input. The SYNC output,
which indicates the instant of frequency change at the
output at the end of the pipeline delay, is generated in
this block.
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 48-bit parallel accumulator,
generating a new sum in every clock cycle. A carry
input (CARRY IN) allows the resolution of the
accumulator to be expanded by means of an auxiliary
NCO or phase accumulator. The overflow signal is
discarded (and is available at the CARRY OUT pin),
since the required output is the modulo (248) sum only.
This represents the modulo (2
π) phase angle.
SINE LOOKUP TABLE BLOCK
This block is the sine memory. The 13 most significant
bits from the Phase Accumulator are used to address
this memory to generate the 12-bit OUT11-0 outputs.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low.
When RESET goes low, all registers including the 48-
bit input buffer are cleared within 30 nsecs. The data
on the OUT
11-0 bus will then be invalid for 6 clock
cycles, and thereafter will remain at the value
corresponding to zero phase, i.e., 2049 (801H), until a
new frequency is loaded into the
-Phase register with
a LDSTB command after the RESET returns to a logic
one.
CIRCUIT DESCRIPTION
The sine and cosine functions are generated from the
13 most significant bits of the phase accumulator. The
frequency of the NCO is determined by the number
stored in the
-Phase register which may be
programmed by an eight-bit microprocessor.
The frequency programming capability of the NCO is
analogous to sampling a sine wave where the
sampling function is the clock. If the output frequency
is very low with respect to the clock (< fc /8096), then
the NCO output will sequence through each of the
8096 states of the sine function.
As the output
frequency is increased with respect to the clock the sine
function will appear to be more discontinuous since
there will be fewer samples in each cycle. At the
Nyquist limit, when the output frequency is exactly
half the clock, the output waveform reduces to a
square wave. The practical upper limit of the NCO
output frequency is about 40% of the clock frequency
because spurious components created by sampling,
which are at a frequency greater than half the clock
frequency, become difficult to remove by filtering.
The phase noise of the NCO output signal may be
determined by knowing the phase noise of the clock
signal input, and the ratio of the output frequency to
the clock frequency. This ratio squared times the phase
noise power of the clock specified in a given
bandwidth is the phase noise power that may be
expected in that same bandwidth relative to the output
frequency.
The NCO achieves its high operating frequency by
making extensive use of pipelining in its architecture.
The pipeline delays within the NCO represent 20 clock
cycles. This effectively limits the minimum possible
frequency switching period of the NCO. After new
frequency data is entered, the load command is given.
After the 20 cycle pipeline delay, the output will
instantaneously switch frequency while maintaining
phase coherence. After this, the next new frequency
may be entered. If a 50 MHz clock were utilized, the
NCO could be continuously switched between
programmed frequencies with a minimum practical
average switching time of about 0.4
sec.
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