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参数资料
| 型号： | STEL-1175+125/CM |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 11/14页 |
| 文件大小： | 253K |
| 代理商： | STEL-1175+125/CM |
STEL-1175+125
6
PHSEL. The phase of the NCO output will change 12
rising clock edges after the PHLD command, due to
pipeline delays.
CIN
The Carry Input is an arithmetic carry to the least
significant bit of the Phase Accumulator. Normal
operation of the NCO requires that CIN be set at a logic
0. When CIN is set at a logic 1 the effective value of the
-Phase register is increased by one. This allows the
resolution of the accumulator to be expanded for higher
frequency resolution by connecting the COUT pin of the
lower order NCO to this input.
SINE
When the SINE input signal is set low the output signal
appearing on the OUT pin will be a cosine function and
when it is set high the DDS output will be a sine function.
After a reset the device will always start at a phase angle of
zero, irrespective of the status of the SINE input. In this
way, by using two devices, one set in the sine mode and
the other set in the cosine mode, quadrature outputs may
be obtained. The quadrature phase relationship of the two
outputs will be maintained at all times provided the two
devices are operated from common RESET, FRLD and
CLOCK signals. The use of phase modulation will, of
course, modify this relationship, unless the devices are also
phase modulated together.
ROUND
The ROUND input controls the precision of the
OUT11-0 output. When the ROUND input is set high, the
sine or cosine signals appearing on the OUT11-0 bus are
accurate to 12 bits. In some instances it may be desirable
to use only the 8 MSBs of this output. In such
circumstances the signals appearing on the OUT11-0 bus
can be rounded to present a more accurate 8-bit
representation of the signal on OUT11-4 by setting the
ROUND input low.
PHCLK
The register at the PHASE11-0 outputs allow the data
appearing on these lines to be strobed and frozen on the
rising edges of the Phase Clock input. For continuous
operation the PHCLK line and the CLOCK line should
be tied together. When the PHASE11-0 outputs are not
used PHCLK should be set low.
OUTPUT SIGNALS
OUT11-0
The signal appearing on the OUT11-0 output bus is derived
from the 13 most significant bits of the Phase
Accumulator. The 12-bit sine or cosine function is
presented in offset binary format. When the phase
modulation is zero and the SINE input is set high, the
value of the output for a given phase value follows the
relationship:
OUT11-0=2047 x sin (360 x (phase+0.5)/8192)°+2048
The result is accurate to within 1 LSB. When the phase
accumulator is zero, e.g., after a reset, the decimal value of
the output is 2049 (801H). However, when ROUND is
set low, the value appearing on the OUT11-0 output will be
rounded and will follow the relationship:
OUT11-4=127 x sin (360 x (phase+0.5)/8192)°+128
The data appearing on the OUT3-0 outputs will not be
meaningful under these circumstances.
When the phase modulation is zero and the SINE input is
set low, the value of the output for a given phase value
follows the relationship:
OUT11-0=2047 x cos (360 x (phase+0.5)/8192)°+2048
The result is accurate to within 1 LSB. When the phase
accumulator is zero, e.g., after a reset, the decimal value of
the output is 4095 (FFFH). However, when ROUND is
set low, the value appearing on the OUT11-0 outputs will
be rounded and will follow the relationship:
OUT11-4=127 x cos (360 x (phase+0.5)/8192)°+128
The data appearing on the OUT3-0 output will not be
meaningful under these circumstances.
PHASE11-0
The 12 MSBs of the Phase ALU output are available on
the PHASE11-0 lines. This signal is clocked on the rising
edges of the PHCLK line.
COUT
Each time the value of the phase accumulator exceeds the
maximum value that can be represented by a 32 bit number
the Carry Out signal goes high for one clock cycle.
FSYNC
The Frequency Sync output indicates the instant in time
when a frequency change made at the inputs affects the
OUT11-0 signals. The normally high FSYNC output goes
low for one clock cycle 18 clock cycles after an FRLD
command to indicate the end of the pipeline delay and the
start of the new steady state condition.
PSYNC
The Phase Sync output indicates the instant in time when
a phase change made at the inputs affects the OUT11-0
signals. The normally high PSYNC output goes low for
one clock cycle 11 clock cycles after a PHLD command,
to indicate the end of the pipeline delay and the start of the
new steady state condition.
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