参数资料
型号: STEL-1175+125/CM
厂商: INTEL CORP
元件分类: 数字信号处理外设
英文描述: 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC68
封装: PLASTIC, LCC-68
文件页数: 5/14页
文件大小: 253K
代理商: STEL-1175+125/CM
13
STEL-1175+125
Care must be taken in interfacing the STEL-1175 with
the DAC. The clock to output delay in the STEL-1175 is
typically 4 nS, but does change with processing variations,
voltage, temperature, and loading. The circuit design must
take this delay into account so that the input to the DAC is
stable at the instant it is clocked into the DAC. The hold
time of the DAC must be less than the minimum clock to
output delay. The set-up time of the DAC must be less
than the clock period minus the maximum clock to output
delay.
STEL-1175 TO DAC INTERFACE
TYPICAL SCHEMATIC DIAGRAM
For example, for 125 MHz, the set-up of the DAC must
be less than 2 nS and the hold time less than 2 nS. For 80
MHz operation, the set-up time of the DAC must be less
than 6.5 nS and the hold time less than 2 nS. This allows
operation with most commercial DACs, such as the Harris
HI5721.
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