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参数资料
| 型号： | STEL-1175+125/CM |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 2/14页 |
| 文件大小： | 253K |
| 代理商： | STEL-1175+125/CM |
STEL-1175+125
10
NCO PHASE CHANGE SEQUENCE
2. PHSEL=1. BUS LOADING.
WRSTB
ADDR 3-0
DATA
7-0
OUT 11-0
PHLD
PSYNC
CLOCK
CSEL
DON'T CARE
12 CLOCK
EDGES
OLD PHASE
NEW PHASE
DON'T CARE
t SU
t HD
t WR
t SU
t W
HIGH-SPEED FREQUENCY CHANGE
The frequency of the STEL-1175 NCO can be changed as
rapidly as 25% of the clock frequency. This is done by
synchronizing the writing to the two -Phase Buffer
Registers, and updating both every eight clock cycles. The
timing for this procedure is shown below. Each -Phase
Buffer Register is loaded while the contents of the other
are being transferred into the -Phase Register. The
sequence for a load cycle begins on the rising edge of the
clock following a falling edge of FRLD. In the diagram on
page 11, -Phase Buffer Register A is being loaded in
cycles 1 through 4, while the contents of -Phase Buffer
Register B are being transferred, because FRSEL was low
during the falling edge of FRLD. The reverse process
happens during cycles 5 through 8, and the process then
repeats starting in cycle 9. The FRLD signal can be used
to clock a bistable latch to generate the FRSEL signal.
The maximum update rate is 25%.
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| STEL-1175+125/MC | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CQCC68 |
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| STEL-1176/CM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Numeric-Controlled Oscillator |
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