参数资料
型号: STM32F100R6T6B
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 24 MHz, RISC MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, ROHS COMPLAINT, LQFP-64
文件页数: 61/86页
文件大小: 1200K
代理商: STM32F100R6T6B
Electrical characteristics
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Doc ID 16455 Rev 5
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
SPI characteristics(1)
1.
Remapped SPI1 characteristics to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
12
MHz
Slave mode
12
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)
(2)
2.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4tPCLK
ns
th(NSS)
NSS hold time
Slave mode
2tPCLK
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, fPCLK = 24 MHz,
presc = 4
50
60
tsu(MI)
tsu(SI)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
Data input hold time
Master mode
5
th(SI)
Slave mode
4
ta(SO)
(2)(3)
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time Slave mode, fPCLK = 24 MHz
0
3tPCLK
tdis(SO)
(2)(4)
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode
2
10
tv(SO)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
Data output valid time
Master mode (after enable
edge)
5
th(SO)
Data output hold time
Slave mode (after enable edge)
15
th(MO)
Master mode (after enable
edge)
2
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