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参数资料
型号： STM32L152CBT6DTR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP48
封装： 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-48
文件页数： 82/106页
文件大小： 1417K
代理商： STM32L152CBT6DTR
STM32L151xx, STM32L152xx
Electrical characteristics
Doc ID 17659 Rev 1
77/106
6.3.14
Communications interfaces
I
2C interface characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 9.
The line I
2C interface meets the requirements of the standard I2C communication protocol
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled,
but is still present.
The I
2C characteristics are described in Table 42. Refer also to Section 6.3.11: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 42.
I2C characteristics
Symbol
Parameter
Standard mode I2C(1)
1.
Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2.
fPCLK1 must be higher than 2 MHz to achieve standard mode IC frequencies. It must be higher than 4 MHz
to achieve fast mode IC frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum IC
fast mode clock.
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0(3)
3.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0(4)
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
Start condition hold time
4.0
0.6
s
tsu(STA)
Repeated Start condition
setup time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
1.3
μs
Cb
Capacitive load for each bus
line
400
pF
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