参数资料
型号: STM32L152CBT6DTR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-48
文件页数: 84/106页
文件大小: 1417K
代理商: STM32L152CBT6DTR
STM32L151xx, STM32L152xx
Electrical characteristics
Doc ID 17659 Rev 1
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 9.
Refer to Section 6.3.11: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 44.
SPI characteristics(1)
1.
Remapped SPI1 characteristics to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
16
MHz
Slave mode
16
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
TBD
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
tsu(NSS)
(2)
2.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4tPCLK
ns
th(NSS)
NSS hold time
Slave mode
2tPCLK
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, fPCLK = 16 MHz,
presc = 4
TBD
tsu(MI)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
Data input hold time
Master mode
5
th(SI)
Slave mode
4
ta(SO)
(2)(3)
3.
Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
data.
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)
4.
Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the
data in Hi-Z.
Data output disable time
Slave mode
TBD
tv(SO)
Data output valid time
Slave mode (after enable edge)
TBD
tv(MO)
Data output valid time
Master mode (after enable edge)
TBD
th(SO)
Data output hold time
Slave mode (after enable edge)
TBD
Master mode (after enable edge)
TBD
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