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| 型号： | SUD50N10-18P-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V DPAK |
| 标准包装： | 1 |
| 系列： | TrenchFET® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 50A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 18.5 毫欧 @ 15A，10V |
| Id 时的 Vgs(th)（最大）： | 5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 75nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 2600pF @ 50V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252，（D-Pak） |
| 包装： | 标准包装 |
| 其它名称： | SUD50N10-18P-GE3DKR |
SUD50N10-18P-GE3
Vishay Siliconix
SPECIFICATIONS (T J = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
V DS Temperature Coefficient
V GS(th) Temperature Coefficient
V DS
? V DS /T J
? V GS(th) /T J
V GS = 0 V, I D = 250 μA
I D = 250 μA
100
110
- 12.5
V
mV/°C
Gate-Source Threshold Voltage
V GS(th)
V DS = V GS , I D = 250 μA
2.5
5
V
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
I GSS
I DSS
I D(on)
V DS = 0 V, V GS = ± 20 V
V DS = 100 V, V GS = 0 V
V DS = 100 V, V GS = 0 V, T J = 125 °C
V DS ?? 5 V, V GS = 10 V
50
± 100
1
50
nA
μA
A
Drain-Source On-State Resistance a
Forward Transconductance a
R DS(on)
g fs
V GS = 10 V, I D = 15 A
V DS = 15 V, I D = 15 A
0.0150
33
0.0185
?
S
Dynamic b
Input Capacitance
C iss
2600
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
C oss
C rss
Q g
Q gs
Q gd
V DS = 50 V, V GS = 0 V, f = 1 MHz
V DS = 50 V, V GS = 10 V, I D = 50 A
230
80
48
16
13
75
pF
nC
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
R g
t d(on)
t r
t d(off)
t f
f = 1 MHz
V DD = 50 V, R L = 1 ?
I D ? 50 A, V GEN = 10 V, R g = 1 ?
1.6
12
10
18
8
2.5
20
20
35
15
?
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode
Pulse Diode Forward Current a
I S
I SM
T C = 25 °C
50
100
A
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
V SD
t rr
Q rr
t a
t b
I S = 15 A
I F = 50 A, dI/dt = 100 A/μs, T J = 25 °C
0.85
80
160
57
23
1.5
120
240
V
ns
nC
ns
Notes:
a. Pulse test; pulse width ? 300 μs, duty cycle ? 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 65717
S12-1958-Rev. C, 13-Aug-12
For technical questions, contact: pmostechsupport@vishay.com
www.vishay.com
2
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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