参数资料
| 型号： | T89C51CC01UA-SLSIM |
| 厂商： | Atmel |
| 文件页数： | 119/123页 |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU FLASH 32K 44PLCC |
| 标准包装： | 27 |
| 系列： | AT89C CAN |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | CAN，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 1.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 配用： | AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN |
| 其它名称： | T89C51CC01UASLSIM |
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2010 Microchip Technology Inc.
DS41303G-page 95
PIC18F2XK20/4XK20
6.5
Writing to Flash Program Memory
The programming block size is 16, 32 or 64 bytes,
depending on the device (See Table 6-1). Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 6-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 16, 32
or 64 times, depending on the device, for each pro-
gramming operation. All of the table write operations
will essentially be short writes because only the holding
registers are written. After all the holding registers have
been written, the programming operation of that block
of memory is started by configuring the EECON1 reg-
ister for a program memory write and performing the
long write sequence.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
Read 64 bytes into RAM.
2.
Update data values in RAM as necessary.
3.
Load Table Pointer register with address being
erased.
4.
Execute the block erase procedure.
5.
Load Table Pointer register with address of first
byte being written.
6.
Write the 16, 32 or 64 byte block into the holding
registers with auto-increment.
7.
Set the EECON1 register for the write operation:
set EEPGD bit to point to program memory;
clear the CFGS bit to access program memory;
set WREN to enable byte writes.
8.
Disable interrupts.
9.
Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 6-3.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all holding registers
before executing a long write operation.
TABLAT
TBLPTR = xxxxYY
(1)
TBLPTR = xxxx01
TBLPTR = xxxx00
Write Register
TBLPTR = xxxx02
Program Memory
Holding Register
8
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
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