参数资料
型号: T89C51CC01UA-SLSIM
厂商: Atmel
文件页数: 63/123页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
标准包装: 27
系列: AT89C CAN
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: CAN,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名称: T89C51CC01UASLSIM
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 153
dsPIC33F
REGISTER 8-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-1
R/W-0
ROI
DOZE<2:0>
DOZEN(1)
FRCDIV<2:0>
bit 15
bit 8
R/W-0
R/W-1
U-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1
= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0
= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits(3)
000
= FCY/1 (default)
001
= FCY/2
010
= FCY/4
011
= FCY/8
100
= FCY/16
101
= FCY/32
110
= FCY/64
111
= FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1)
1
= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0
= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000
= FRC divide by 1
001
= FRC divide by 2
010
= FRC divide by 4
011
= FRC divide by 8 (default)
100
= FRC divide by 16
101
= FRC divide by 32
110
= FRC divide by 64
111
= FRC divide by 256
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)(2)
00
= Output/2
01
= Output/4
10
= Reserved (defaults to output/4)
11
= Output/8
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000
= Input/2
00001
= Input/3
11111
= Input/33
Note 1:
This bit is cleared when the ROI bit is set and an interrupt occurs.
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