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参数资料
| 型号： | TAS5122DFDR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 37 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56 |
| 封装： | POWERPAD, PLASTIC, TSSOP-56 |
| 文件页数： | 5/22页 |
| 文件大小： | 313K |
| 代理商： | TAS5122DFDR |
TAS5122
SLES088C AUGUST 2003 REVISED NOVEMBER 2003
www.ti.com
13
PWM_xP forces the high side MOSFET ON until it
eventually runs out of BST capacitor energy. Putting the
device in this condition should be avoided.
In practice this means that the DVDD-to-PWM processor
should be stable and initialization should be completed
before RESET is deasserted to the power stage.
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other PWM processor device. The pin is open-drain with
an internal pullup to DVDD.
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
SD
RESET
DESCRIPTION
0
Not used
0
1
Device in protection mode, i.e., UVP and/or OC
and/or OT error
1(2)
0
Device set high-impedance (Hi-Z), SD forced high
1
Normal operation
(2) SD is pulled high when RESET is asserted low independent
of chip state (i.e., protection mode). This is desirable to
maintain compatibility with some TI PWM processors.
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup to DVDD.
OTW
DESCRIPTION
0
Junction temperature higher than 125
°C
1
Junction temperature lower than 125
°C
Overall Reporting
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
Table 1. Error Signal Decoding
OTW
SD
DESCRIPTION
0
Overtemperature error (OTE)
0
1
Overtemperature warning (OTW)
1
0
Overcurrent (OC) or undervoltage (UVP) error
1
Normal operation, no errors/warnings
Chip Protection
The TAS5122 protection function is implemented in a
closed loop with, for example, a system controller or other
TI PWM processor device. The TAS5122 contains three
individual systems protecting the device against misuse.
All of the error events covered result in the output stage
being set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
Overcurrent (OC) Protection
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Demodulation Filter Design in the
Application Information section of this data sheet for
design constraints.
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125
°C. The OT protection circuit is shared by all
half-bridges.
Undervoltage (UV) Protection
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
Reset Function
The function of the reset input is twofold:
D Reset is used for re-enabling operation after a
latching error event (PMODE1).
D Reset is used for disabling output stage
switching (mute function).
The error latch is cleared on the falling edge of reset and
normal operation is resumed when reset goes high.
PROTECTION MODE
Latching Shutdown on All Errors (PMODE1)
In latching shutdown mode, all error situations result in a
permanent shutdown (output stage Hi-Z). Re-enabling can
be done by toggling the RESET pin.
Autorecovery (AR) After Errors (PMODE0)
In autorecovery mode (PMODE0) the TAS5122 is 100%
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time period
the device auto-recovers, i.e., operation is automatically
resumed provided that the system is fully operational.
The auto-recovery timing is set by counting PWM input
cycles, i.e. the timing is relative to the switching frequency.
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