- 您现在的位置：买卖IC网 > PDF目录98164 > TAS5518PAGR (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP64 PDF资料下载
参数资料
| 型号： | TAS5518PAGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 12/105页 |
| 文件大小： | 1514K |
| 代理商： | TAS5518PAGR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页
Introduction
6
SLES115 — August 2004
TAS5518
TERMINAL
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NO.
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NAME
7
VRD_PLL
P
Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-F low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
8
AVSS_PLL
P
Analog ground for PLL. This terminal should reference the same ground as power
terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be
minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground distribution techniques to achieve a quiet ground reference
at this terminal.
9
AVDD_PLL
P
3.3-V analog power supply for PLL This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter, this
terminal should be bypassed to AVSS_PLL with a 0.1-F low-ESR capacitor.
10
VBGAP
P
Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.
Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
11
RESET
DI
5 V
Pull up
System reset input, active low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that restores the
TAS5518 to its default conditions, sets the valid output low, and places the PWM
in the hard mute (M) state. Master volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 45 ms. device
initialization and set the volume at mute.
12
HP_SEL
DI
5 V
Pull up
Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected –
headphone is off.
13
PDN
DI
5 V
Pull up
Power down, active low. PDN powers down all logic and stops all clocks whenever
a logic low is applied. The internal parameters are preserved through a power down
cycle, as long as a RESET is not active. The duration for system recovery from
power down is 100 ms.
14
MUTE
DI
5 V
Pull up
Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a
logic high) The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
15
DVDD
P
Digital power 3.3-V supply for digital core and most of I/O buffers
16
DVSS
P
Digital ground for digital core and most of I/O buffers
17
VR_DPLL
P
Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital PLL logic. A 0.1F low ESR capacitor should be
connected between this terminal and DVSS_CORE. This terminal must not be
used to power external devices.
18
OSC_CAP
AO
Oscillator capacitor
19
XTL_OUT
AO
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the
recommended crystal type.
20
XTL_IN
AI
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the
recommended crystal type.
21
RESERVED
Connect to digital ground
22
RESERVED
Connect to digital ground
23
RESERVED
Connect to digital ground
24
SDA
DIO
5 V
I2C serial control data interface input / output
25
SCL
DI
5 V
I2C serial control clock input output
26
LRCLK
DI
5 V
Serial audio data left / right clock (sampling rate clock)
27
SCLK
DI
5 V
Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data
bit clock that is supplied to the serial bit clock to other I2S bus.
相关PDF资料 |
PDF描述 |
|---|---|
| TAS5518PAGG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5601DCAG4 | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56 |
| TAS5601DCARG4 | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56 |
| TAS5601DCAR | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56 |
| TAS5601DCA | 20 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TAS5518PAGRG4 | 功能描述:音频 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS5538 | 制造商:TI 制造商全称:Texas Instruments 功能描述:TAS5612L-TAS5614LDDVEVM |
| TAS5538DGG | 制造商:TI 制造商全称:Texas Instruments 功能描述:TAS5612L-TAS5614LDDVEVM |
| TAS5538DGGR | 制造商:Texas Instruments 功能描述:audio processor |
| TAS5548 | 制造商:TI 制造商全称:Texas Instruments 功能描述:8-Channel HD Compatible Audio Processor with ASRC and PWM Output |
发布紧急采购，3分钟左右您将得到回复。