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| 型号： | TAS5518PAGR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 14/105页 |
| 文件大小： | 1514K |
| 代理商： | TAS5518PAGR |
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Introduction
8
SLES115 — August 2004
TAS5518
TERMINAL
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NO.
DESCRIPTION
TERMIN-
ATION
5-V
TOLERANT
I/O
NAME
63
MCLK
DI
5 V
Pulldown MCLK is a 3.3-V clock master clock input. The input frequency of this clock can
range from 4 MHz to 50 MHz.
64
RESERVED
Connect to digital ground
NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output
2. All pullups are 200-A weak pullups and all pulldowns are 200-A weak pull downs. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pull ups must be able to sink 200 A, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must
be able to source 200 A, while maintaining a logic ‘1’ drive level.
3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
4. 13.5-MHz crystal (HCM49)
1.4
TAS5518 Functional Description
Figure 14 shows the TAS5518 functional structure. The next sections describe the TAS5518 functional
blocks:
Power Supply
Clock, PLL, and Serial Data Interface
Serial Control Interface
Device Control
Digital Audio Processor (DAP)
Pulse Width Modulation (PWM) Processor
1.4.1 Power Supply
The power supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5518. The analog supply supports the analog PLL, while digital supplies support
the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control
(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.
1.4.2 Clock, PLL, and Serial Data Interface
The TAS5518 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts
MCLK, SCLK, and LRCLK as inputs only.
The TAS5518 uses the external crystal to provide a time base for:
Continuous data and clock error detection and management
Automatic data rate detection and configuration
Automatic MCLK rate detection and configuration (automatic bank switching)
Supporting I2C operation/ communication while MCLK is absent
The TAS5518 automatically handles clock errors, data rate changes, and master clock frequency changes
without requiring intervention from an external system controller. This feature significantly reduces system
complexity and design.
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