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参数资料
| 型号： | TC1068MQR |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封装： | QSOP-16 |
| 文件页数： | 13/14页 |
| 文件大小： | 76K |
| 代理商： | TC1068MQR |
8
SMBus Thermal Sensor with
External Diode Input
TC1068
TC1068-1 2/8/99
2001 Microchip Technology Inc. DS21352A
Standby Mode Operation
STBY#
Chip Stop Bit
One Shot?
Operating Mode
0
Don’t Care
Standby
1
0
Don’t Care
Normal
1
No
Standby
1
Yes
Normal
(1 Conversion Only,
then Standby)
SMBus SLAVE ADDRESS
The two pins ADD1 and ADD0 are tri-state input pins
which determine the 7-bit SMBus slave address of the
TC1068. The address is latched during POR. The allowable
addresses are summarized in the following table.
SERIAL PORT OPERATION
The Serial Clock input (SCL) and bi-directional data port
(SDAT) form a 2-wire bi-directional serial port for program-
ming and interrogating the TC1068. The following conven-
tions are used in the bus architecture in the followingtable.
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TC1068
always operates as a slave. The serial protocol is illustrated
in Figure 3. All data transfers have two phases; all bytes are
transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes
a Read/Write selection bit. Each access must be terminated
by a Stop Condition (STOP). A convention called
Acknowl-
edge (ACK) confirms receipt of each byte. Note that SDA
can change only during periods when SCL is LOW (SDA
changes while SCL is High are reserved for Start and Stop
conditions.)
TC1068 Serial Bus Conventions
Term
Explanation
Transmitter
The device sending data to the bus.
Receiver
The device receiving data from the bus.
Master
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
Slave
The device addressed by the master.
Start
A unique condition signaling the beginning of
a transfer indicated by SDA falling (High –
Low) while SCL is high.
Stop
A unique condition signaling the end of a
transfer indicated by SDA rising (Low – High)
while SCL is high.
ACK
A receiver acknowledges the receipt of each
byte with this unique condition. The receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock
pulse for the ACK cycle.
Busy
Communication is not possible because the
bus is in use.
NOT Busy
When the bus is idle, both SDA and SCL
will remain high.
Data Valid
The state of SDA must remain stable during
the High period of SCL in order for a data bit to
be considered valid. SDA only changes state
while SCL is low during normal data transfers
(see Start and Stop conditions).
Address Decode Table
ADD0
ADD1
SMBus Address
0
0011 000
0
open (3-state)
0011 001
0
1
0011 010
open (3-state)
0
0101 001
open (3-state)
0101 010
open (3-state)
1
0101 011
1
0
1001 100
1
open (3-state)
1001 101
1
1001 110
Start Condition (START)
The TC1068 continuously monitors the SDA and SCL
lines for a start condition (a High to Low transition of SDA
while SCL is High), and will not respond until this condition
is met.
Address Byte
Immediately following the Start Condition, the host must
transmit the address byte to the TC1068. The states of
ADD1 and ADD0 during power-up determine the 7-bit
SMBus address for the TC1068. The 7-bit address transmit-
ted in the serial bit stream must match for the TC1068 to
respond with an Acknowledge (indicating the TC1068 is on
the bus and ready to accept data). The eighth bit in the
Address Byte is a Read-Write Bit. This bit is 1 for a read
operation or 0 for a write operation.
Acknowledge (ACK)
Acknowledge (ACK) provides a positive handshake
between the host and the TC1068. The host releases SDA
after transmitting eight bits, then generates a ninth clock
cycle to allow the TC1068 to pull the SDA line Low to
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