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参数资料
| 型号： | TC835C/PI |
| 元件分类： | ADC |
| 英文描述： | 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28 |
| 封装： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件页数： | 3/26页 |
| 文件大小： | 420K |
| 代理商： | TC835C/PI |
2007 Microchip Technology Inc.
DS21478C-page 11
TC835
5.4
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion
time
to
exceed
20,000
clock
pulses,
the
OVERRANGE output is set to a logic "1." The
overrange output register is set when BUSY goes low,
and is reset at the beginning of the next reference
integration phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low at the next signal integration
phase.
5.6
POLARITY Output
A positive input is registered by a logic "1" polarity
signal. The POLARITY bit is valid at the beginning of
Reference Integrate and remains valid until determined
during the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the
signal polarity determined correctly. This is useful in
null applications.
5.7
Digit Drive Outputs
Digit drive signals are positive going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock
pulses wide, except D5, which is 201 clock pulses wide.
All five digits are scanned continuously, unless an over-
range condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse
until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2, B1 are
positive-true logic signals. The data bits become active
simultaneously with the digit drive signals. In an
overrange condition, all data bits are at a logic "0" state.
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