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参数资料
| 型号： | TC835C/PI |
| 元件分类： | ADC |
| 英文描述： | 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28 |
| 封装： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件页数： | 5/26页 |
| 文件大小： | 420K |
| 代理商： | TC835C/PI |
2007 Microchip Technology Inc.
DS21478C-page 13
TC835
TABLE 6-2:
LINE FREQUENCY VS.
CLOCK FREQUENCY
The conversion rate is easily calculated:
EQUATION 6-3:
6.3
Power Supplies and Grounds
6.3.1
POWER SUPPLIES
The TC835 is designed to work from ±5V supplies. For
single +5V operation, a ICL7135 can provide a –5V
supply.
6.3.2
GROUNDING
Systems should use separate digital and analog
ground systems to avoid loss of accuracy.
6.4
High-Speed Operation
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3 s delay, and at a clock
frequency of 200 kHz (5 s period), half of the first
reference integrate clock period is lost in delay. This
means that the meter reading will change from 0 to 1
with a 50 V input, 1 to 2 with 150 V, 2 to 3 at 250 V,
etc. This transition at midpoint is considered desirable
by most users, however, if the clock frequency is
increased appreciably above 200 kHz, the instrument
will flash "1" on noise peaks even when the input is
shorted.
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator
need not be a limitation. Since the nonlinearity and
noise do not increase substantially with frequency,
clock rates of up to ~1 MHz may be used. For a fixed
clock frequency, the extra count or counts caused by
comparator delay will be a constant and can be
subtracted out digitally.
The clock frequency may be extended above 200 kHz
without this error, however, by using a low-value
resistor in series with the integrating capacitor. The
effect of the resistor is to introduce a small pedestal
voltage onto the integrator output at the beginning of
the reference integrate phase. By careful selection of
the ratio between this resistor and the integrating
resistor (a few tens of ohms in the recommended
circuit), the comparator delay can be compensated and
the maximum clock frequency extended by approxi-
mately a factor of 3. At higher frequencies, ringing and
second-order breaks will cause significant nonlineari-
ties in the first few counts of the instrument.
The minimum clock frequency is established by leak-
age on the auto zero and reference capacitors. With
most devices, measurement cycles as long as 10 sec-
onds give no measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0 “Typical Applications”,
Typical Applications. The multiplexed output means
that if the display takes significant current from the logic
supply, the clock should have good PSRR.
6.5
Zero Crossing Flip-Flop
The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse
and half-clock pulse have died down. False zero cross-
ings caused by clock pulses are not recognized. Of
course, the flip flop delays the true zero crossing by up
to one count in every instance. If a correction were not
made, the display would always be one count too high.
Therefore, the counter is disabled for one clock pulse
at the beginning of the reference integrate (de-inte-
grate) phase. This one-count delay compensates for
the delay of the zero crossing flip flop and allows the
correct number to be latched into the display. Similarly,
a one-count delay at the beginning of auto zero gives
an overload display of 0000 instead of 0001. No delay
occurs during signal integrate, so that true ratiometric
readings result.
Oscillator Frequency
(kHz)
Line Frequency Rejection
60Hz
50Hz
400Hz
50.000
53.333
—
66.667
—
80.000
—
83.333
—
100.000
125.000
—
133.333
—
166.667
—
200.000
—
250.000
Reading 1/sec =
Clock Frequency (Hz)
4000
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