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参数资料
| 型号： | TC86R4600 |
| 厂商： | Toshiba Corporation |
| 英文描述： | 64 Bit RISC Microprocessor(64位精简指令集微处理器) |
| 中文描述： | 64位RISC微处理器（64位精简指令集微处理器） |
| 文件页数： | 8/30页 |
| 文件大小： | 267K |
| 代理商： | TC86R4600 |
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TC86R4600 64-bit RISC Microprocessor
6
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
Data TLB
The R4600 also incorporates a 4-entry data TLB. Each entry
maps a 4KB page. The data TLB improves performance by
allowing data address translation to occur in parallel with data
address translation. When a miss occurs on a data address transla-
tion, the DTLB is Tlled from the JTLB. The DTLB reTll is
pseudo-LRU: the least recently used entry of the least recently
used half is Tlled. The operation of the DTLB is invisible to the
user.
Figure 6. Kernel Mode Virtual Addressing (32-bit mode)
0xFFFFFFFF
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
0xE0000000
0xDFFFFFFF
Supervisor virtual address space
(sseg)
Mapped, 0.5GB
0xC0000000
0xBFFFFFFF
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0xA0000000
0x9FFFFFFF
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x80000000
0x7FFFFFFF
Kernel user virtual address space
(kuseg)
Mapped, 2.0GB
0x00000000
Cache Memory
In order to keep the R4600s high-performance pipeline full and
operating efTciently, the R4600 incorporates on-chip instruction
and data caches that can be accessed in a single processor cycle.
Each cache has its own 64-bit data path and can be accessed in
parallel. For example, the cache subsystem provides the integer
and oating-point units with an aggregate bandwidth of 1.6GB
per second at a system clock frequency of 50MHz.
Instruction Cache
The R4600 incorporates a two-way set associative on-chip
instruction cache. This virtually indexed, physically tagged cache
is 16KB in size and is protected with word parity.
Because the cache is virtually indexed, the virtual-to-physi-
cal address translation occurs in parallel with the cache access,
thus further increasing performance by allowing these two opera-
tions to occur simultaneously. The tag holds a 24-bit physical
address and valid bit, and is parity protected.
The instruction cache is 64-bits wide, and can be reTlled or
accessed in a single processor cycle. Instruction fetches require
only 32 bits per cycle, for a peak instruction bandwidth of
400MB/sec. Sequential accesses take advantage of the 64-bit
fetch to reduce power dissipation, and cache miss reTll writes 64
bits per cycle to minimize the cache miss penalty. The line size is
eight instructions (32 bytes) to maximize performance.
Data Cache
For fast, single cycle data access, the R4600 includes a 16KB on-
chip data cache that is two-way set associative with a Txed 32-
byte (eight words) line size.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and phys-
ically tagged to allow simultaneous address translation and data
cache access
The normal write policy is writeback, which means that a
store to a cache line does not immediately cause memory to be
updated. This increases system performance by reducing bus traf-
Tc and eliminating the bottleneck of waiting for each store opera-
tion to Tnish before issuing a subsequent memory operation.
Software can, however, select write-through on a per-page basis
when it is appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the
R4600 executes a store instruction, this single-entry buffer gets
written with the store data while the tag comparison is per-
formed. If the tag matches, then the data is written into the data
cache in the next cycle that the data cache is not accessed (the
next non-load cycle). The store buffer allows the R4600 to exe-
cute a store every processor cycle and to perform back-to-back
stores without penalty.
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