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参数资料
| 型号： | TC86R4600 |
| 厂商： | Toshiba Corporation |
| 英文描述： | 64 Bit RISC Microprocessor(64位精简指令集微处理器) |
| 中文描述： | 64位RISC微处理器（64位精简指令集微处理器） |
| 文件页数： | 9/30页 |
| 文件大小： | 267K |
| 代理商： | TC86R4600 |
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TC86R4600 64-bit RISC Microprocessor
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
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7
Write buffer
Writes to external memory, whether cache miss writebacks or
stores to uncached or write-through addresses, use the on-chip
write buffer. The write buffer holds up to four 64-bit address and
data pairs. The entire buffer is used for a data cache writeback
and allows the processor to proceed in parallel with memory
update. For uncached and write-through stores, the write buffer
signiTcantly increases performance over the R4000 family of
processors.
System Interface
The R4600 supports a 64-bit system interface that is compatible
with the R4000PC system interface. This interface operates from
two clocks provided by the R4600,
RClock[1:0]
. The TClock and RClock frequencies are
derived from the internal (2x input clock) clock by dividing by:
8, 6, 4, 3, or 2.
The interface consists of a 64-bit Address/Data bus with 8
check bits and a 9-bit command bus protected with parity. In
addition, there are 8 handshake signals and 6 interrupt inputs.
The interface has a simple timing speciTcation and is capable of
transferring data between the processor and memory at a peak
rate of 400MB/sec at 50MHz.
Figure 6 on page 7 shows a typical system using the R4600.
In this example two banks of DRAMs are used to supply and
accept data with a
DDxxDDxx
data pattern.
TClock[1:0]
and
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the R4600 and the rest of the system.
It is protected with an 8-bit parity check bus, SysADC.
The system interface is conTgurable to allow easier interfac-
ing to memory and I/O systems of varying frequencies. The data
rate and the bus frequency at which the R4600 transmits data to
the system interface are programmable via boot time mode con-
trol bits (note, however that early versions of the R4600 will Tx
the system interface clock divisor at 2). Also, the rate at which
the processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no read or
write buffering or a faster, high performance interface can be
designed to communicate with the R4600. Again, the system
designer has the exibility to make these price/performance
trade-offs.
System Command Bus
The R4600 interface has a 9-bit System Command (SysCmd)
bus. The command bus indicates whether the SysAD bus carries
an address or data. If the SysAD carries an address, then the
SysCmd bus also indicates what type of transaction is to take
place (for example, a read or write). If the SysAD carries data,
then the SysCmd bus also gives information about the data (for
example, this is the last data word transmitted, or the cache state
of this data line is clean exclusive). The SysCmd bus is bidirec-
tional to support both processor requests and external requests to
the R4600. Processor requests are initiated by the R4600 and
responded to by an external device. External requests are issued
by an external device and require the R4600 to respond.
The R4600 supports one to eight byte and block transfers on
the SysAD bus. In the case of a sub-doubleword transfer, the
low-order three address bits gives the byte address of the transfer,
and the SysCmd bus indicates the number of bytes being trans-
ferred.
Handshake Signals
There are eight handshake signals on the system interface. Two
of these, RdRdy and WrRdy are used by an external device to
indicate to the R4600 whether it can accept a new read or write
transaction. The R4600 samples these signals before de-asserting
the address on read and write requests.
Figure 7. Typical Desktop System Block Diagram
R4600
Memory I/O
Controller
DRAM
DRAM
Control
Address
SCSI
ENET
72
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