
TC90A80N/F
2002-12-04
7
IC Control Specifications
Functions and characteristics of this IC are set using the I2C bus.
The data transfer format conforms to the Philips I2C bus format.
When reset signal is applied, the following DATA bits are all cleared to 0.
Data transfer format
S
Slave address (8 bits)
A
DATA1
A
DATA2
A
DATA3
A
DATA4
A
P
Slave address: B4H S: Start condition, A: Acknowledgement, P: Stop condition
Outline of I2C bus format
I2C bus transfers data between ICs using two lines: data (SDA) and clock (SCL).
The I2C bus starts according to the start condition and ends according to the stop condition.
The start condition is satisfied if SDA changes from High to Low when SCL is High.
The stop condition is satisfied if SDA changes from Low to High when SCL is High.
The length of data to be transferred is 8 bits. Data are transferred via the SDA line. An acknowledge (ACK) bit is required after a
data byte. The bus line must be pulled up to the power supply level using a resistor. When SCL is High, data must not be
changed.
I2C bus control signal timing
Characteristics
Symbol
Min
Max
Unit
SCL clock frequency
fSCL
0
100
kHz
Hold time to satisfy start condition
tHD; STA
4.0
―
s
SCL clock Low period
tLOW
4.7
―
s
SCL clock High period
tHIGH
4.0
―
s
Data hold time
tHD; DAT
0
3.45
s
Data setup time
tSU; DAT
250
―
ns
SDA/SCL signal rise time
tr
―
1000
ns
SDA/SCL signal fall time
tf
―
300
ns
Stop condition setup time
tSU; STO
4.0
―
s
Bus free time between stop and start conditions
tBUF
4.7
―
s
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Date
Clock
Start Condition
tHD; STA
tLOW
tHIGH
tSU; DAT
tHD; DAT
tSU; STO
tBUF
tr
tf
Stop Condition
Don’t change the data while clock is in High level.