参数资料
型号: TDF8599TD
厂商: NXP SEMICONDUCTORS
元件分类: 音频/视频放大
英文描述: 70 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36
封装: PLASTIC, SOT851-2, HSOP-36
文件页数: 13/53页
文件大小: 329K
代理商: TDF8599TD
TDF8599_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
20 of 53
NXP Semiconductors
TDF8599
I2C-bus controlled dual channel class-D power amplier
Remark: DC load detection identies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has nished and once the amplier is in Operating mode.
The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load detection enable bit IB2[D2] must be reset after the DC load protection cycle to
release any amplier hang-up. Once the DC load detection cycle has nished, DC load
detection can be restarted by toggling the DC load detection enable bit IB2[D2]. However,
this can only be used if both amplier channels have not been enabled with bit IB1[D1] or
detection enabled” for detailed information.
8.6.2.2
Recommended start-up sequence with DC load detection enabled
The ow diagram (Figure 20) illustrates the TDF8599’s ability to perform a DC load
detection without starting the ampliers. After a DC load detection cycle nishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predened number of cycles (COUNTMAX), if the
DC load detection cycle nishes with an invalid detection.
Depending on the application needs, the invalid DC load detection cycle can be handled
as follows:
the amplier can be started without DC load detection
the DC load detection loop can be executed again
A valid DC load detection cycle does not affect the normal amplier start-up timing.
Table 12.
Interpretation of DC load detection bits
DC load bits DB1[D4] and DB2[D4]
OCP bits DB1[D3] and DB2[D3]
Description
0
speaker load
0
1
shorted load
1
0
open load
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