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| 型号： | THS1041CDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, SOIC-28 |
| 文件页数： | 25/41页 |
| 文件大小： | 777K |
| 代理商： | THS1041CDWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
31
www.ti.com
APPLICATION INFORMATION
initial clamp acquisition time (continued)
Initial acquisition can be performed in two ways:
D Pulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below) is negligible, initial
acquisition is complete when the total clamped (CLAMP = high) time equals TACQ.
D Pulling the CLAMP pin high for the required acquisition time before starting normal operation. This method
is faster, though possibly less convenient for the user to implement.
clamp droop
The charging currents drawn by the sample-and-hold switched capacitor input can charge or discharge CIN,
causing the dc voltage at AIN+ to drift towards the dc bias voltage at AIN during the time between clamp pulses.
This effect is called clamp droop.
Voltage droop is a function of the AIN+ and AIN input currents to the THS1041, IIN, and the time between clamp
intervals, tD:
V
DROOP [
I
IN
C
IN
t
d
(approximate)
Worst case droop between clamping intervals occurs for maximum input bias current. Maximum input current
is IINFS, which occurs when the input level is at its maximum or minimum.
For example, at 40 MSPS IINFS is approximately 20 A for a 2-V input range at AIN (assuming 2 V appear across
RIN2—see driving the sample and hold reference inputs to calculate RIN2). Note that IINFS may vary from this
by
±30% because of processing variations and voltage dependencies. Designs should allow for this variation.
If the time td between clamping intervals is 63.5 s and CIN is 1 F, then the maximum clamp level droop between
clamp pulses is
V
DROOP
(max)
+ 20 mA 1 mF
63.5
ms + 1.25 mV (approximate, ignoring 30% tolerance)
+ 0.62 LSB at PGA gain + 1, 2 V ADC references
If this droop is greater than can be tolerated in the application, then increase CIN to slow the droop and hence
reduce the voltage change between clamp pulses.
If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly
worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors as these have higher
leakage currents than nonpolarized capacitor types. Electrolytic and tantalum capacitors also tend to have
higher parasitic inductance, which can cause problems at high input frequencies.
steady-state clamp voltage error
During the clamp pulse (CLAMP = high), the dc voltage on AIN is refreshed from the clamp voltage. Provided
that droop is not excessive, clamping fully reverses the effect of droop. However, using very short clamp pulses
with long intervals between pulses (td) can result in a steady-state voltage difference, VCOS, between the dc
voltage at AIN and V(Clamp).
Figure 47 shows the approximate voltage waveform at AIN resulting from a a large clamp droop during td and
clamp voltage reacquisition during the clamp pulse time, tc.
(17)
(18)
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| THS1041CPW | 功能描述:模数转换器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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