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参数资料
型号： THS4215DGN
厂商： TEXAS INSTRUMENTS INC
元件分类： 音频／视频放大
英文描述： 1 CHANNEL, VIDEO AMPLIFIER, PDSO8
封装： POWERPAD, GREEN, PLASTIC, MSOP-8
文件页数： 19/47页
文件大小： 1197K
代理商： THS4215DGN
E
O
+
E 2
NI
) IBNRS
2
) 4kTRS )
I
BIRf
NG
2
)
4kTR
f
NG
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
100 k
1 M
10 M
100 M
1 G
Capacitive Load - Hz
Normalized
Gain
-
dB
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
R(ISO) = 15
CL = 50 pF
VS =±5 V
R(ISO) = 10
CL = 100 pF
R(ISO) = 25
CL = 10 pF
THS4211
THS4215
SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com
Dividing this expression by the noise gain [NG= (1 +
Rf/Rg) ] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased
Figure 88. Isolation Resistor Diagram
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
BOARD LAYOUT
considered,
this
capacitive
load
introduces
an
additional pole in the signal path that can decrease
Achieving
optimum
performance
with
a
high
the phase margin. When the primary considerations
frequency amplifier like the THS4211 requires careful
are frequency response flatness, pulse response
attention to board layout parasitics and external
fidelity, or distortion, the simplest and most effective
component types.
solution is to isolate the capacitive load from the
Recommendations that optimize performance include
feedback loop by inserting a series isolation resistor
the following:
between the amplifier output and the capacitive load.
1. Minimize parasitic capacitance to any ac
This does not eliminate the pole from the loop
ground for all of the signal I/O pins. Parasitic
response, but rather shifts it and adds a zero at a
capacitance on the output and inverting input pins
higher frequency. The additional zero acts to cancel
can cause instability: on the noninverting input, it
the phase lag from the capacitive load pole, thus
can react with the source impedance to cause
increasing the phase margin and improving stability.
unintentional band limiting. To reduce unwanted
The Typical Characteristics show the recommended
capacitance, a window around the signal I/O pins
isolation resistor vs capacitive load and the resulting
should be opened in all of the ground and power
frequency response at the load. Parasitic capacitive
planes around those pins. Otherwise, ground and
loads greater than 2 pF can begin to degrade the
power planes should be unbroken elsewhere on
performance of the THS4211. Long PCB traces,
the board.
unmatched cables, and connections to multiple
2. Minimize the distance (< 0.25”) from the
devices can easily cause this value to be exceeded.
power supply pins to high frequency 0.1-F
Always consider this effect carefully, and add the
decoupling capacitors. At the device pins, the
recommended series resistor as close as possible to
ground and power plane layout should not be in
the
THS4211
output
pin
(see
Board
Layout
close proximity to the signal I/O pins. Avoid
Guidelines).
narrow power and ground traces to minimize
The criterion for setting this R(ISO) resistor is a
inductance between the pins and the decoupling
maximum bandwidth, flat frequency response at the
capacitors. The power supply connections should
load. For a gain of +2, the frequency response at the
always be decoupled with these capacitors.
output pin is already slightly peaked without the
Larger (2.2-F to 6.8-F) decoupling capacitors,
capacitive load, requiring relatively high values of
effective at lower frequency, should also be used
R(ISO) to flatten the response at the load. Increasing
on the main supply pins. These may be placed
the noise gain also reduces the peaking.
somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
space
26
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Copyright 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
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