17
20
19
18
GND
16
CH.2 IN B
CH.3 IN B
15
I2C-A0
SDA
VS+ 11
14
13
12
SCL
CH. 3 SAG
I2C-A1
CH.1 IN B
CH.2 IN A
CH.3 IN A
CH.1 IN A
NC
CH.3 OUT
CH. 2 SAG
CH.2 OUT
CH. 1 SAG
CH.1 OUT
NC
1
2
3
4
5
6
7
8
9
10
+
DAC /
Encoder
(THS8200)
Y’
P’B
P’R
External
Input
Y’
P’B
P’R
R
HDTV
480i
576i
480p
576p
720p
1080i
1080p
3.3V
75 W
Y’
Out
P’
Out
B
P’
Out
R
75 W
0.1 F
m
0.01 F
m
+Vs
100 F
m
1 F
m
1 F
m
47 F
m
47 F
m
47 F
m
33 F
m
33 F
m
33 F
m
*(SeeNote A)
*
I C
Controller
2
ACSTC
ACBias
DC+135mV
SLOS479B
– OCTOBER 2005 – REVISED MARCH 2011
The internal resistor values were chosen to optimize the system while using the 47-
μF and 33-μF capacitors, and
to approximate the performance of a single 330-
μF capacitor. These capacitors can be a different value if
desired, but the characteristics of the system are altered accordingly. For example, if 22-
μF capacitors are used
for both sections, then there are increases in line tilt and field tilt. For some systems, this may be considered
acceptable (for example, 720p Y' signals with the associated faster line rates). Using larger values, such as 68
μF and 47 μF respectively, decreases field time distortion even further, and approaches the performance of a
single 470-
μF capacitor.
It is important to note that the dc gain is about 2.55 V/V. Thus, if the input has a dc bias, the output dc bias is
2.55 times the input. For example, this results in an output bias point of 355 mV for the dc + 135 mV shift.
Additionally, if the ac bias input mode is selected, the dc operating point is VS+/4 × 2.55, or 2.1 V with 3.3-V
supply and 3.2 V with 5-V supply. This additional offset should not hinder the performance of the THS7303
because there is still plenty of voltage headroom between the dc operating point and the rail-to-rail output
capability.
One possible concern about this configuration is that the low-frequency gain enhancement may cause saturation
of the signal when low power-supply voltages (such as 3 V) are used. The internal resistors were chosen to
minimize the low-frequency gain so that saturation is minimized. Other SAG correction devices have much higher
low-frequency gain (10 dB or higher), which when coupled with low power-supply voltages, can easily create
clipping on the output of the amplifier, both dynamically and at dc. Other SAG correction devices do not use a
resistor in series with the SAG pin. Neglecting this resistor can result in a large Q enhancement causing possible
saturation issues. These systems typically require much larger capacitor values to minimize this problem, which
ultimately minimizes the benefits of SAG correction.
Figure 67 shows a SAG-corrected configuration for the THS7303. If a S-Video chroma channel is being
configured, there is no reason for SAG correction because the coupling capacitor is typically small at 0.1
μF.
Thus, tying the output pin directly to the SAG output pin is recommended along with a 0.1-
μF capacitor.
Note that increasing the gain of the THS7303 can be easilly accomplished by using the SAG pin. Simply placing
a resistor, RSAG, between the SAG pin and GND increases the gain by forming a resistor divider on the signal
feedback path. The resulting gain becomes VOUT/VIN = 2.553 + (1268 / (150 + RSAG)).
A.
If the SAG correction capacitors are more than 15 mm from the THS7313, add a 0.01
μF capacitor as shown.
Figure 67. Typical Y
'P'BP'R System Driving SAG Corrected AC-Coupled Video Lines
32
Copyright
2005–2011, Texas Instruments Incorporated