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参数资料
| 型号： | TLC32046IFN |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| 封装： | PLASTIC, CC-28 |
| 文件页数： | 19/56页 |
| 文件大小： | 274K |
| 代理商： | TLC32046IFN |
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2–12
Table 2–4. AIC Responses to Improper Conditions
IMPROPER CONDITION
AIC RESPONSE
TA register + TA
′ register = 0 or 1
Reprogram TX(A) counter with TA register value
g
TA register – TA
′ register = 0 or 1
g( )
g
TA register + TA
′ register < 0
MODULO 64 arithmetic is used to ensure that a positive value is loaded into
TX(A) counter, i.e., TA register + TA
′ register + 40 HEX is loaded into TX(A)
counter.
RA register + RA
′ register = 0 or 1
Reprogram RX(A) counter with RA register value
g
RA register – RA
′ register = 0 or 1
g( )
g
RA register + RA
′ register = 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into
RX(A) counter, i.e., RA register + RA
′ register + 40 HEX is loaded into RX(A)
counter.
TA register = 0 or 1
AIC is shut down. Reprogram TA or RA registers after a reset.
g
RA register = 0 or 1
gg
TA register < 4 in word mode
The AIC serial port no longer operates. Reprogram TA or RA registers after
g
TA register < 5 in byte mode
gg
g
a reset.
RA register < 4 in word mode
RA
it
5 i bt
d
RA register < 5 in byte mode
TB register < 15
Reprogram TB register with 12 HEX
RB register < 15
Reprogram RB register with 12 HEX
AIC and DSP cannot communicate
Hold last DAC output
2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A
′ register result is too small. When incrementally
adjusting the conversion period via the A + A
′ register options, the designer should not violate this
requirement (see Figure 2–4).
t2 – t1 ≤ 1/25 kHz
t2
t1
Ongoing Conversion
Frame Sync
(FSX or FSR)
Figure 2–4. Conversion Times Too Close Together
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs – Asynchronous Operation
When incrementally adjusting the conversion period via the A + A
′ or A – A′ register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B can be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2–5).
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