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参数资料
| 型号： | TLC32047IFN |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | Wide-Band Analog Interface Circuit |
| 中文描述： | 宽带模拟接口电路 |
| 文件页数： | 27/61页 |
| 文件大小： | 303K |
| 代理商： | TLC32047IFN |
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2–9
2.15.2
A/D OR D/A MSB
Primary DX Word Bit Pattern
1st bit sent
↓
D15
1st bit sent of 2nd byte
↓
D8
D7
A/D or D/A LSB
↓
D3
D2
D14
D13
D12
D11
D10
D9
D6
D5
D4
D1
D0
Table 2–2. Primary DX Serial Communication Protocol
FUNCTIONS
D1
D0
D15 (MSB)-D2
→
DAC Register.
TA
→
TX(A), RA
→
RX(A) (see Figure 2–1).
TB
→
TX(B), RB
→
RX(B) (see Figure 2–1).
D15 (MSB)-D2
→
DAC Register.
TA+TA
′
→
TX(A), RA+RA
′
→
RX(A) (see Figure 2–1).
TB
→
TX(B), RB
→
RX(B) (see Figure 2–1).
The next D/A and A/D conversion period is changed by the addition of TA
′
and RA
′
master clock cycles,
in which TA
′
and RA
′
can be positive, negative, or zero (refer to Table 2–4, AIC Responses to Improper
Conditions).
D15 (MSB)-D2
→
DAC Register.
TA–TA
′
→
TX(A), RA–RA
′
→
RX(A) (see Figure 2–1).
TB
→
TX(B), RB
→
RX(B) (see Figure 2–1).
The next D/A and A/D conversion period is changed by the subtraction of TA
′
and RA
′
master clock cycles,
in which TA
′
and RA
′
can be positive, negative, or zero (refer to Table 2–4, AIC Responses to Improper
Conditions).
D15 (MSB)-D2
→
DAC Register.
TA
→
TX(A), RA
→
RX(A) (see Figure 2–1).
TB
→
TX(B), RB
→
RX(B) (see Figure 2–1).
After a delay of four shift cycles, a secondary transmission follows to program the AIC to operate in the
desired configuration. In the telephone interface mode, data on DATA-DR is routed to DR (Serial Data
Output) during secondary transmission.
0
0
0
1
1
0
1
1
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications)
to the AIC initiates secondary communications upon completion of the primary communications. When the
primary communication is complete, FSX remains high for four shift clock cycles and then goes low and initiates
the secondary communication. The timing specifications for the primary and secondary communications are
identical. In this manner, the secondary communication, if initiated, is interleaved between successive primary
communications. This interleaving prevents the secondary communication from interfering with the primary
communications and DAC timing. This prevents the AIC from skipping a DAC output. FSR is not asserted during
secondary communications activity. However, in the dual-word (telephone interface) mode, FSD is asserted
during secondary communications but not during primary communications.
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相关代理商/技术参数 |
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|---|---|
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