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参数资料
| 型号： | TLV1571IPWG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | GREEN, TSSOP-24 |
| 文件页数： | 23/33页 |
| 文件大小： | 627K |
| 代理商： | TLV1571IPWG4 |
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TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLV1571
TLV1578
AGND
21
25
Analog ground
AIN
23
27
I
ADC analog input (used as single analog input channel for TLV1571)
AVDD
22
26
Analog supply voltage, 2.7 V to 5.5 V
CH0 – CH7
–
1– 4,
29–32
I
Analog input channels
CLK
4
8
I
External clock input
CS
1
5
I
Chip select. A logic low on CS enables the TLV1571/ TLV1578.
CSTART
18
22
I
Hardware sample and conversion start input. The falling edge of CSTART starts sampling and
the rising edge of CSTART starts conversion.
DGND
5
9
Digital ground
DVDD
6
10
Digital supply voltage, 2.7 V to 5.5 V
D0 – D7
8 –12,
13 –15
12 –16,
17–19
I/O
Bidirectional 3-state data bus
D8/A0
16
20
I/O
Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0
and CR1 for initialization.
D9/A1
17
21
I/O
Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0
and CR1 for initialization.
INT/EOC
7
11
O
End-of-conversion/interrupt
MO
28
O
On-chip MUX analog output
NC
24
Not connected
RD
3
7
I
Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM
20
24
I
Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be
grounded.
REFP
19
23
I
Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by
the difference between the voltage applied to REFP and REFM.
WR
2
6
I
Write data. A rising edge on the WR latches in configuration data when CS is low. When using
software conversion start, a rising edge on WR also initiates an internal sampling start pulse.
When WR is tied to ground, the ADC in nonprogrammable (hardware configuration mode).
相关PDF资料 |
PDF描述 |
|---|---|
| TLV1571CDWG4 | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1578CDARG4 | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 |
| TLV1571IDW | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1571CPW | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1571IDWR | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV1572 | 制造商:TI 制造商全称:Texas Instruments 功能描述:2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN |
| TLV1572CD | 功能描述:模数转换器 - ADC 10bit A/D RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDG4 | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDR | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDRG4 | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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