- 您现在的位置：买卖IC网 > PDF目录98250 > TLV1571IPWG4 (TEXAS INSTRUMENTS INC) 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 PDF资料下载
参数资料
| 型号： | TLV1571IPWG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | GREEN, TSSOP-24 |
| 文件页数： | 6/33页 |
| 文件大小： | 627K |
| 代理商： | TLV1571IPWG4 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
software START conversion (continued)
system clock source
The TLV1571/TLV1578 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used
for most conversion subtasks. The source of SYSCLK is programmable via control register zero bit 5. The
source of SYSCLK is changed at the rising edge of WR of the cycle when CR0.D5 is programmed.
internal clock (CR0.D5 = 0, SYSCLK = internal OSC)
The TLV1571/TLV1578 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of
SYSCLK, the internal clock starts with a delay (one half of the OSC period max) after the falling edge of the
conversion trigger (either WR, RD, or CSTART). The OSC speed can be set to 10
± 1 MHz or 20 ± 2 MHz by
setting register bit CR1.6.
external clock (CR0.D5 = 1, SYSCLK = external clock)
The TLV1571/TLV1578 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from
1 MHz to 20 MHz.
host processor interface
The TLV1571/TLV1578 provides a generic high-speed parallel interface that is compatible with
high-performance DSPs and general-purpose microprocessors. The interface includes D(0–9), INT/EOC, RD,
and WR.
output format
The data output format is unipolar (code 0 to 1023) when the device is operated in single-ended input mode.
The output code format can be either binary or twos complement by setting register bit CR1.D3.
power up and initialization
After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV1571/TLV1578 requires
two write cycles to configure the two control registers. The first conversion after the device has returned from
the power-down state may be invalid and should be disregarded.
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than
±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
相关PDF资料 |
PDF描述 |
|---|---|
| TLV1571CDWG4 | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1578CDARG4 | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 |
| TLV1571IDW | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1571CPW | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV1571IDWR | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV1572 | 制造商:TI 制造商全称:Texas Instruments 功能描述:2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN |
| TLV1572CD | 功能描述:模数转换器 - ADC 10bit A/D RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDG4 | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDR | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV1572CDRG4 | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
发布紧急采购，3分钟左右您将得到回复。