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| 型号： | TLV2556MPWREPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, TSSOP-20 |
| 文件页数： | 24/37页 |
| 文件大小： | 705K |
| 代理商： | TLV2556MPWREPG4 |
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LSB Out First
Bipolar Output Format
Reference
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Because the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000...0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111...1). The conversion result of (VREF+ + VREF–)/2 is
a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100...0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011...1). The
conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000...0). The MSB is interpreted as the sign bit. The
bipolar data format is related to the unipolar format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
The device has a built-in reference with a programmable level of 2.048 V or 4.096 V. If the internal reference is
used, REF+ is set to 2.048 V or 4.096 V and REF– is set to analog GND. An external reference can also be used
through two reference input pins, REF+ and REF–, if the reference source is programmed as external. The
voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a
full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not
exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The
digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input
signal is equal to or lower than REF–.
30
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2556-EP
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