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参数资料
| 型号： | TLV320ADC3101IRGER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封装： | GREEN, PLASTIC, VQFN-24 |
| 文件页数： | 46/84页 |
| 文件大小： | 1363K |
| 代理商： | TLV320ADC3101IRGER |
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SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Page 0 / Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Offset = 0 BCLKs. Offset is measured with respect to WCLK rising edge in DSP mode.(1)
0000 0001: Offset = 1 BCLKs
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
(1)
Usage controlled by page 0 / register 38, bit D0
Page 0 / Register 29: ADC Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved. Do not write any value other than reset value.
D3
R/W
0
0: BCLK is not inverted (valid for both primary and secondary BCLK).
1: BCLK is inverted (valid for both primary and secondary BCLK).
D2
R/W
0
0: BCLK and WCLK active even with codec powered down: disabled (valid for both primary and
secondary BCLK)
1: BCLK and WCLK active even with codec powered down: enabled (valid for both primary and
secondary BCLK)
D1–D0
R/W
10
00: Reserved. Do not use.
01: Reserved. Do not use.
10: BDIV_CLKIN = ADC_CLK (generated on-chip)
11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
Page 0 / Register 30: BCLK N Divider
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: BCLK N divider is powered down.
1: BCLK N divider is powered up.
D6–D0
R/W
000 0001
000 0000: CLKOUT divider N = 128
000 0001: CLKOUT divider N = 1
000 0010: CLKOUT divider N = 2
...
111 1110: CLKOUT divider N = 126
111 1111: CLKOUT divider N = 127
Page 0 / Register 31: Secondary Audio Interface Control 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved. Do not write any value other than reset value.
D6–D5
R/W
00
00: Secondary BCLK is obtained from GPIO1 pin.
01: Secondary BCLK is obtained from GPIO2 pin.
10 – 11: Reserved. Do not use.
D4–D3
R/W
00
00: Secondary WCLK is obtained from GPIO1 pin.
01: Secondary WCLK is obtained from GPIO2 pin.
10 – 11: Reserved. Do not use.
D2-D1
R/W
00
Reserved. Do not use.
D0
R
0
Reserved. Do not write any value other than reset value.
Page 0 / Register 32: Secondary Audio Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R
0000
Reserved. Do not write any value other than reset value.
D3
R/W
0
0: Primary BCLK is used for audio interface and clocking.
1: Secondary BCLK is used for audio interface and clocking.
D2
R/W
0
0: Primary WCLK is used for audio interface and clocking.
1: Secondary WCLK is used for audio interface and clocking.
D1–D0
R
00
Reserved. Do not write any value other than reset value.
50
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TLV320ADC3101
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