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参数资料
| 型号： | TLV320ADC3101IRGER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封装： | GREEN, PLASTIC, VQFN-24 |
| 文件页数： | 51/84页 |
| 文件大小： | 1363K |
| 代理商： | TLV320ADC3101IRGER |
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www.ti.com...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Page 0 / Register 53: DOUT (OUT Pin) Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R
000
Reserved. Do not write any value other than reset value.
D4
R/W
1
0: DOUT bus keeper enabled
1: DOUT bus keeper disabled
D3–D1
R/W
001
000: DOUT disabled (output buffer powered down)
001 DOUT = primary DOUT output for codec interface
010: DOUT = general-purpose output
011: DOUT = CLKOUT output
100: DOUT = INT1 output
101: DOUT = INT2 output
110: DOUT = secondary BCLK output for codec interface
111: DOUT = secondary WCLK output for codec interface
D0
R/W
0
DOUT value = 0 when D3–D1 are programmed to "010" (general-purpose output)
DOUT value = 1 when D3–D1 are programmed to "010" (general-purpose output)
Page 0 / Register 54 Through Page 0 / Register 56: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
XXXX XXXX
Reserved. Do not write to this register.
Page 0 / Register 57: ADC Sync Control 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Default synchronization
1: Custom synchronization
D6–D0
R/W
000 0000
000 0000: Custom synchronization window size = 0 instructions
000 0001: Custom synchronization window size = 2 instructions (±1 instruction)
000 0010: Custom synchronization window size = 4 instructions (±2 instructions)
...
111 1111: Custom synchronization window size = 254 instructions (±127 instructions)
Page 0 / Register 58: ADC Sync Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Custom synchronization target = instruction 0
0000 0001: Custom synchronization target = instruction 2
0000 0010: Custom synchronization target = instruction 4
...
1111 1111: Custom synchronization target = instruction 510
Page 0 / Register 59: ADC CIC Filter Gain Control
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0100
Left CIC filter gain(1)
D3–D0
R/W
0100
Right CIC filter gain(1)
(1)
For proper operation, CIC gain must be
≤ 1.
If AOSR {page 0 /register 20} = 64 and (1
≤ Filter Mode {page 0 / register 61} ≤ 6), then the reset value of 4 results in CIC gain = 1.
Otherwise, the CIC gain = (AOSR/(64 × miniDSP Engine Decimation))4 × 2 (CIC Filter Gain Control) for 0
≤ CIC Filter Gain Control ≤ 12,
and if CIC Filter Gain Control = 15, CIC gain is automatically set such that for 7
≤ (AOSR/miniDSP Engine Decimation) ≤ 64,
0.5 < CIC gain
≤ 1.
Page 0 / Register 60: Reserved
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
Reserved. Do not write to this register.
Copyright 2008–2009, Texas Instruments Incorporated
55
Product Folder Link(s) :TLV320ADC3101
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