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| 型号： | TLV320AIC31IRHBT |
| 厂商： | Texas Instruments |
| 文件页数： | 13/84页 |
| 文件大小： | 0K |
| 描述： | IC CODEC STEREO AUDIO 32-QFN |
| 标准包装： | 1 |
| 类型： | 立体声音频 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 24 b |
| ADC / DAC 数量： | 2 / 2 |
| 三角积分调变： | 是 |
| S/N 比，标准 ADC / DAC (db)： | 92 / 100 |
| 动态范围，标准 ADC / DAC (db)： | 92 / 100 |
| 电压 - 电源，模拟： | 2.7 V ~ 3.6 V |
| 电压 - 电源，数字： | 1.65 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 配用： | 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31 296-19475-ND - MODULE EVAL FOR TLV320AIC31 |
| 其它名称： | 296-19422-6 |
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DIGITAL AUDIO DATA SERIAL INTERFACE
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA are treated as data for the next incremental
register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next eight clocks the data of the next incremental register.
Audio data are transferred between the host processor and the TLV320AIC31 via the digital audio data serial
interface, or audio bus. The audio bus of the TLV320AIC31 can be configured for left- or right-justified, I2S, DSP,
or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within
the TDM mode. These modes are all MSB-first, with data width programmable as 16-, 20-, 24-, or 32-bits. In
addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either Master or Slave
mode for flexible connectivity to a wide variety of processors
The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or
a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC
sampling frequencies.
The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed in two further modes: continuous transfer mode and 256-clock mode. In
continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,
so in general the number of bit clocks per frame will be two times the data width. For example, if data width is
chosen as 16-bit, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode will be
used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used.
These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × FS or 64 × FS. In
the cases of 20-bit and 24-b-t data width in master mode, the bit clocks generated in each frame will not all be of
equal period, due to the device not having a clean 40 × FS or 48 × FS clock signal readily available. The average
frequency of the bit clock signal is still accurate in these cases (being 40 × FS or 48 × FS), but the resulting clock
signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC31 further includes programmability to 3-state the DOUT line during all bit clocks when valid data
are not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio
data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a
single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a 3-state output condition.
20
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC31
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV320AIC31IRHBT | 制造商:Texas Instruments 功能描述:IC CODEC STEREO AUDIO 32-VQFN |
| TLV320AIC31IRHBTG4 | 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC32 | 制造商:BB 制造商全称:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| TLV320AIC32_07 | 制造商:BB 制造商全称:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| TLV320AIC3204 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Ultra Low Power Stereo Audio Codec |
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