参数资料
型号: TLV320AIC31IRHBT
厂商: Texas Instruments
文件页数: 18/84页
文件大小: 0K
描述: IC CODEC STEREO AUDIO 32-QFN
标准包装: 1
类型: 立体声音频
数据接口: PCM 音频接口
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 92 / 100
动态范围,标准 ADC / DAC (db): 92 / 100
电压 - 电源,模拟: 2.7 V ~ 3.6 V
电压 - 电源,数字: 1.65 V ~ 1.95 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 标准包装
配用: 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
其它名称: 296-19422-6
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
When the PLL is enabled,
FSref = (PLLCLK_IN × K × R) / (2048 × P), where
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by register 102, bits D5-D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz
≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz
≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4
≤ J ≤ 55
When the PLL is enabled and D
≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz
≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz
≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4
≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and FSref = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and FSref = 48.0 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Copyright 2006–2008, Texas Instruments Incorporated
25
Product Folder Link(s): TLV320AIC31
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