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参数资料
| 型号： | TMP86CH09NG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, 1.78 MM PITCH, LEAD FREE, PLASTIC, SDIP-32 |
| 文件页数： | 63/120页 |
| 文件大小： | 1743K |
| 代理商： | TMP86CH09NG |
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Page 36
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86FH09ANG
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter-
rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe-
cuted before setting IMF="1".
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL
(003DH, 003CH)
15
14
13
12
11
10
9876543210
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
ILH (003DH)
ILL (003CH)
IL15 to IL2
Interrupt latches
at RD
0: No interrupt request
1: Interrupt request
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
R/W
Interrupt Enable Registers
(Initial value: 00000000 0000***0)
EIRH,EIRL
(003BH, 003AH)
15
14
13
12
11
10
9876
54321
0
EF15
EF14
EF13
EF12
EF11
EF10
EF9
EF8
EF7
EF6
EF5
EF4
IMF
EIRH (003BH)
EIRL (003AH)
EF15 to EF4
Individual-interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
R/W
IMF
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
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